Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1514977704	204310	0	0
RunThenComplete_M	1514977704	2166059	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	204310	0	0
T1	476048	310	0	0
T2	400886	27	0	0
T3	3181	0	0	0
T4	352477	367	0	0
T6	101372	16	0	0
T12	226917	195	0	0
T16	4958	1	0	0
T38	19134	9	0	0
T39	19055	9	0	0
T40	147488	310	0	0
T41	0	390	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	2166059	0	0
T1	476048	5462	0	0
T2	400886	957	0	0
T3	3181	0	0	0
T4	352477	3074	0	0
T6	101372	670	0	0
T12	226917	1090	0	0
T16	4958	3	0	0
T38	19134	31	0	0
T39	19055	31	0	0
T40	147488	5462	0	0
T41	0	5542	0	0