Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	98.08	100.00	100.00			92.31	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	100.00			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.79	100.00	100.00	66.67		92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.21	100.00			100.00	92.86	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_pos_dupcnt.u_pos	66.67			66.67

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
110	1	1
111	1	1
112	1	1
115	1	1
120	1	1
122	1	1
124	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       110
 EXPRESSION (ack_in && ((!ack_out)))
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T5
1	1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (((!ack_in)) && ack_out)
             -----1-----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       112
 EXPRESSION (ack_in && ack_out)
             ---1--    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T15,T5

 LINE       115
 EXPRESSION (g_pos_dupcnt.cnt_incr_en ? (8'(inmask_ones)) : (8'(OutW)))
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T4,T15,T5
1	1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T26,T64
1	1	Covered	T1,T2,T6

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T2,T6

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
TERNARY	115	2	2	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
IF	122	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	(g_pos_dupcnt.cnt_incr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T2,T6
2'b10	Covered	T1,T2,T3
2'b11	Covered	T4,T15,T5
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T2,T6
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T2,T6
FlushSend	-	0	Covered	T1,T2,T6
default	-	-	Not Covered

	LineNo.	Expression
-1-:	122	if ((pos_with_input > 8'(OutW)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	1514977704	476233	0	942
DataOStableWhenPending_A	1514977704	660264	0	942
ExFlushValid_M	1514977704	204313	0	0
ExcessiveDataStored_A	1514977704	45850	0	0
ExcessiveMaskStored_A	1514977704	45850	0	0
FlushFollowedByDone_A	1514977704	204313	0	942
ValidIDeassertedOnFlush_M	1514977704	349331	0	0
ValidOAssertedForStoredDataGTEOutW_A	1514977704	33109271	0	0
ValidOPairedWidthReadyI_A	1514977704	660264	0	0
g_byte_assert.InputDividedBy8_A	942	942	0	0
g_byte_assert.OutputDividedBy8_A	942	942	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	1514977704	74247940	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	1514977704	33248771	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	1514977704	33248771	0	0
gen_mask_assert.ContiguousOnesMask_M	1514977704	74247940	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	476233	0	942
T4	352477	12	0	1
T5	128982	4460	0	1
T10	0	6818	0	0
T11	0	10	0	0
T15	199064	3	0	1
T17	0	4310	0	0
T25	0	7381	0	0
T26	140871	832	0	1
T27	235619	0	0	1
T39	19055	0	0	1
T40	147488	0	0	1
T41	851363	0	0	1
T42	102644	0	0	1
T43	659503	0	0	1
T58	0	6250	0	0
T77	0	8	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	660264	0	942
T5	128982	4557	0	1
T10	0	6241	0	0
T17	56378	4513	0	1
T25	0	6627	0	0
T26	140871	832	0	1
T43	659503	0	0	1
T45	3373	0	0	1
T58	0	6485	0	0
T59	0	1483	0	0
T64	721209	7805	0	1
T80	0	15375	0	0
T93	31663	0	0	1
T94	603010	0	0	1
T106	0	5376	0	0
T107	919508	0	0	1
T108	505368	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	204313	0	0
T1	476048	310	0	0
T2	400886	27	0	0
T3	3181	0	0	0
T4	352477	367	0	0
T6	101372	16	0	0
T12	226917	195	0	0
T16	4958	1	0	0
T38	19134	9	0	0
T39	19055	9	0	0
T40	147488	310	0	0
T41	0	390	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	45850	0	0
T4	352477	8	0	0
T5	128982	657	0	0
T10	0	300	0	0
T11	0	7	0	0
T15	199064	3	0	0
T17	0	755	0	0
T24	0	9	0	0
T25	0	405	0	0
T26	140871	91	0	0
T27	235619	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T43	659503	0	0	0
T44	0	18	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	45850	0	0
T4	352477	8	0	0
T5	128982	657	0	0
T10	0	300	0	0
T11	0	7	0	0
T15	199064	3	0	0
T17	0	755	0	0
T24	0	9	0	0
T25	0	405	0	0
T26	140871	91	0	0
T27	235619	0	0	0
T39	19055	0	0	0
T40	147488	0	0	0
T41	851363	0	0	0
T42	102644	0	0	0
T43	659503	0	0	0
T44	0	18	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	204313	0	942
T1	476048	310	0	1
T2	400886	27	0	1
T3	3181	0	0	1
T4	352477	367	0	1
T6	101372	16	0	1
T12	226917	195	0	1
T16	4958	1	0	1
T38	19134	9	0	1
T39	19055	9	0	1
T40	147488	310	0	1
T41	0	390	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	349331	0	0
T1	476048	580	0	0
T2	400886	51	0	0
T3	3181	0	0	0
T4	352477	688	0	0
T6	101372	28	0	0
T12	226917	370	0	0
T16	4958	1	0	0
T38	19134	18	0	0
T39	19055	18	0	0
T40	147488	580	0	0
T41	0	730	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33109271	0	0
T1	476048	68812	0	0
T2	400886	17719	0	0
T3	3181	0	0	0
T4	352477	42719	0	0
T6	101372	11768	0	0
T12	226917	12965	0	0
T16	4958	0	0	0
T27	0	4677	0	0
T38	19134	100	0	0
T39	19055	100	0	0
T40	147488	68812	0	0
T41	0	95772	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	660264	0	0
T5	128982	4557	0	0
T10	0	6241	0	0
T17	56378	4513	0	0
T25	0	6627	0	0
T26	140871	832	0	0
T43	659503	0	0	0
T45	3373	0	0	0
T58	0	6485	0	0
T59	0	1483	0	0
T64	721209	7805	0	0
T80	0	15375	0	0
T93	31663	0	0	0
T94	603010	0	0	0
T106	0	5376	0	0
T107	919508	0	0	0
T108	505368	0	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	33248771	0	0
T1	476048	69082	0	0
T2	400886	17743	0	0
T3	3181	0	0	0
T4	352477	43040	0	0
T6	101372	11780	0	0
T12	226917	13140	0	0
T16	4958	0	0	0
T27	0	4746	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	69082	0	0
T41	0	96112	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	74247940	0	0
T1	476048	160203	0	0
T2	400886	41480	0	0
T3	3181	1	0	0
T4	352477	98084	0	0
T6	101372	27751	0	0
T12	226917	31305	0	0
T16	4958	0	0	0
T38	19134	235	0	0
T39	19055	246	0	0
T40	147488	158319	0	0
T41	0	224394	0	0