Unified Coverage Report :: Module :: kmac_core

Module : kmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		100.00	92.86	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core	98.57	100.00	100.00		100.00	92.86	100.00

---

Module Instance : tb.dut.u_kmac_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		100.00	92.86	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.85	100.00	100.00	100.00	100.00	93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_key_slicer[0].u_key_slicer	100.00	100.00					100.00
gen_key_slicer[1].u_key_slicer	100.00	100.00					100.00
u_key_index_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	6	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
375	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Module : kmac_core

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T109,T110
1	0	Covered	T2,T6,T12

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T109,T110

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

---

FSM Coverage for Module : kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T2,T6,T12
StKmacFlush	208	Covered	T2,T6,T12
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T2,T6,T12
StTerminalError	241	Covered	T3,T20,T21

transitions	Line No.	Covered	Tests
StKey->StKmacMsg	194	Covered	T2,T6,T12
StKey->StTerminalError	241	Covered	T21,T67,T35
StKmacFlush->StKmacIdle	218	Covered	T2,T6,T12
StKmacFlush->StTerminalError	241	Covered	T56
StKmacIdle->StKey	181	Covered	T2,T6,T12
StKmacIdle->StTerminalError	241	Covered	T3,T7,T73
StKmacMsg->StKmacFlush	208	Covered	T2,T6,T12
StKmacMsg->StTerminalError	241	Covered	T20,T51,T52

---

Branch Coverage for Module : kmac_core

	Line No.	Total	Covered	Percent
Branches		56	52	92.86
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	4	100.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T2,T6,T12
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T2,T6,T12
StKey	-	0	-	-	Covered	T2,T6,T12
StKmacMsg	-	-	1	-	Covered	T2,T6,T12
StKmacMsg	-	-	0	-	Covered	T2,T6,T12
StKmacFlush	-	-	-	1	Covered	T2,T6,T12
StKmacFlush	-	-	-	0	Covered	T2,T6,T12
StTerminalError	-	-	-	-	Covered	T3,T20,T21
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T109,T110
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T2,T12,T4
L256	Covered	T1,T2,T3
L384	Covered	T1,T4,T40
L512	Covered	T42,T5,T76
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Module : kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	1514977704	6588192	0	0
KeyDataStableWhenValid_M	1514977704	291077141	0	0
KeyLengthStableWhenValid_M	1514977704	291077141	0	0
KmacEnStable_M	1514977704	20644	0	0
MaxKeyLenMatchToKey512_A	942	942	0	0
ModeStable_M	1514977704	31851	0	0
ProcessLatchedCleared_A	1514977704	2	0	0
StrengthStable_M	1514977704	38063	0	0
u_state_regs_A	1514977704	1514786187	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	6588192	0	0
T2	400886	11711	0	0
T3	3181	0	0	0
T4	352477	27816	0	0
T5	0	12094	0	0
T6	101372	7679	0	0
T12	226917	9825	0	0
T15	0	1524	0	0
T16	4958	0	0	0
T26	0	401	0	0
T27	0	3663	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	291077141	0	0
T2	400886	269523	0	0
T3	3181	0	0	0
T4	352477	215035	0	0
T5	0	667256	0	0
T6	101372	605151	0	0
T12	226917	156011	0	0
T15	0	93814	0	0
T16	4958	0	0	0
T26	0	49911	0	0
T27	0	170816	0	0
T38	19134	14683	0	0
T39	19055	14583	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	291077141	0	0
T2	400886	269523	0	0
T3	3181	0	0	0
T4	352477	215035	0	0
T5	0	667256	0	0
T6	101372	605151	0	0
T12	226917	156011	0	0
T15	0	93814	0	0
T16	4958	0	0	0
T26	0	49911	0	0
T27	0	170816	0	0
T38	19134	14683	0	0
T39	19055	14583	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	20644	0	0
T2	400886	13	0	0
T3	3181	0	0	0
T4	352477	163	0	0
T5	0	60	0	0
T6	101372	9	0	0
T12	226917	70	0	0
T15	0	20	0	0
T16	4958	2	0	0
T27	0	31	0	0
T38	19134	1	0	0
T39	19055	1	0	0
T40	147488	0	0	0
T41	851363	0	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	31851	0	0
T2	400886	13	0	0
T3	3181	1	0	0
T4	352477	248	0	0
T6	101372	10	0	0
T12	226917	70	0	0
T15	0	54	0	0
T16	4958	3	0	0
T27	0	32	0	0
T38	19134	1	0	0
T39	19055	1	0	0
T40	147488	0	0	0
T41	851363	0	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	2	0	0
T109	89328	1	0	0
T110	0	1	0	0
T111	391268	0	0	0
T112	397697	0	0	0
T113	128265	0	0	0
T114	1434	0	0	0
T115	623837	0	0	0
T116	1148	0	0	0
T117	333733	0	0	0
T118	617586	0	0	0
T119	22839	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	38063	0	0
T1	476048	2	0	0
T2	400886	18	0	0
T3	3181	2	0	0
T4	352477	270	0	0
T6	101372	8	0	0
T12	226917	97	0	0
T16	4958	2	0	0
T38	19134	2	0	0
T39	19055	2	0	0
T40	147488	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0

Line Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	161	3	3	100.00
ALWAYS	166	30	30	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	252	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
ALWAYS	268	6	6	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	307	6	6	100.00
ALWAYS	338	6	6	100.00
ALWAYS	338	6	6	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
ALWAYS	420	6	6	100.00
CONT_ASSIGN	431	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
153	1	1
161	3	3
166	1	1
168	1	1
169	1	1
171	1	1
173	1	1
174	1	1
176	1	1
178	1	1
180	1	1
181	1	1
183	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
199	1	1
201	1	1
207	1	1
208	1	1
210	1	1
212	1	1
217	1	1
218	1	1
220	1	1
226	1	1
227	1	1
240	1	1
241	1	1
			MISSING_ELSE
251	1	1
252	1	1
253	1	1
254	1	1
258	1	1
260	1	1
265	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
274	1	1
			MISSING_ELSE
287	1	1
307	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
338	1	1
341	1	1
345	1	1
349	1	1
353	1	1
358	1	1
372	1	1
375	1	1
394	1	1
420	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
431	1	1

---

Cond Coverage for Instance : tb.dut.u_kmac_core

	Total	Covered	Percent
Conditions	28	28	100.00
Logical	28	28	100.00
Non-Logical	0	0
Event	0	0

 LINE       180
 EXPRESSION (kmac_en_i && start_i)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       207
 EXPRESSION (process_i || process_latched)
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T109,T110
1	0	Covered	T2,T6,T12

 LINE       251
 EXPRESSION (en_kmac_datapath ? kmac_valid : fifo_valid_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       252
 EXPRESSION (en_kmac_datapath ? kmac_data : fifo_data_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       253
 EXPRESSION (en_kmac_datapath ? kmac_strb : fifo_strb_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       254
 EXPRESSION (en_kmac_datapath ? 1'b0 : msg_ready_i)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       258
 EXPRESSION (en_key_write ? '1 : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       260
 EXPRESSION (en_key_write ? key_sliced : ('{(*adjust*)default:'0}))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       265
 EXPRESSION (kmac_en_i ? kmac_process : process_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

 LINE       270
 EXPRESSION (process_i && ((!process_o)))
             ----1----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T109,T110

 LINE       394
 EXPRESSION (kmac_valid & msg_ready_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T12

 LINE       431
 EXPRESSION (key_index == block_addr_limit)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T12

---

FSM Coverage for Instance : tb.dut.u_kmac_core

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StKey	181	Covered	T2,T6,T12
StKmacFlush	208	Covered	T2,T6,T12
StKmacIdle	183	Covered	T1,T2,T3
StKmacMsg	194	Covered	T2,T6,T12
StTerminalError	241	Covered	T3,T20,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
StKey->StKmacMsg	194	Covered	T2,T6,T12
StKey->StTerminalError	241	Covered	T21,T67,T35
StKmacFlush->StKmacIdle	218	Covered	T2,T6,T12
StKmacFlush->StTerminalError	241	Excluded	T56	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StKmacIdle->StKey	181	Covered	T2,T6,T12
StKmacIdle->StTerminalError	241	Covered	T3,T7,T73
StKmacMsg->StKmacFlush	208	Covered	T2,T6,T12
StKmacMsg->StTerminalError	241	Covered	T20,T51,T52

---

Branch Coverage for Instance : tb.dut.u_kmac_core

	Line No.	Total	Covered	Percent
Branches		56	52	92.86
TERNARY	251	2	2	100.00
TERNARY	252	2	2	100.00
TERNARY	253	2	2	100.00
TERNARY	254	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	2	2	100.00
TERNARY	265	2	2	100.00
IF	161	2	2	100.00
CASE	178	10	10	100.00
IF	240	2	2	100.00
IF	268	4	4	100.00
CASE	307	6	5	83.33
CASE	420	6	5	83.33
CASE	338	6	5	83.33
CASE	338	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	251	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	254	(en_kmac_datapath) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	258	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	(en_key_write) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(kmac_en_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st)
-2-:	180	if ((kmac_en_i && start_i))
-3-:	193	if (sent_blocksize)
-4-:	207	if ((process_i || process_latched))
-5-:	217	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StKmacIdle	1	-	-	-	Covered	T2,T6,T12
StKmacIdle	0	-	-	-	Covered	T1,T2,T3
StKey	-	1	-	-	Covered	T2,T6,T12
StKey	-	0	-	-	Covered	T2,T6,T12
StKmacMsg	-	-	1	-	Covered	T2,T6,T12
StKmacMsg	-	-	0	-	Covered	T2,T6,T12
StKmacFlush	-	-	-	1	Covered	T2,T6,T12
StKmacFlush	-	-	-	0	Covered	T2,T6,T12
StTerminalError	-	-	-	-	Covered	T3,T20,T21
default	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	240	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if ((!rst_ni))
-2-:	270	if ((process_i && (!process_o)))
-3-:	272	if ((process_o || prim_mubi_pkg::mubi4_test_true_strict(done_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T109,T110
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	420	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T2,T12,T4
L256	Covered	T1,T2,T3
L384	Covered	T1,T4,T40
L512	Covered	T42,T5,T76
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

	LineNo.	Expression
-1-:	338	case (key_len_i)

Branches:

-1-	Status	Tests
Key128	Covered	T1,T2,T3
Key192	Covered	T1,T2,T6
Key256	Covered	T1,T2,T6
Key384	Covered	T1,T2,T6
Key512	Covered	T1,T2,T3
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_kmac_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckOnlyInMessageState_A	1514977704	6588192	0	0
KeyDataStableWhenValid_M	1514977704	291077141	0	0
KeyLengthStableWhenValid_M	1514977704	291077141	0	0
KmacEnStable_M	1514977704	20644	0	0
MaxKeyLenMatchToKey512_A	942	942	0	0
ModeStable_M	1514977704	31851	0	0
ProcessLatchedCleared_A	1514977704	2	0	0
StrengthStable_M	1514977704	38063	0	0
u_state_regs_A	1514977704	1514786187	0	0

AckOnlyInMessageState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	6588192	0	0
T2	400886	11711	0	0
T3	3181	0	0	0
T4	352477	27816	0	0
T5	0	12094	0	0
T6	101372	7679	0	0
T12	226917	9825	0	0
T15	0	1524	0	0
T16	4958	0	0	0
T26	0	401	0	0
T27	0	3663	0	0
T38	19134	109	0	0
T39	19055	109	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KeyDataStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	291077141	0	0
T2	400886	269523	0	0
T3	3181	0	0	0
T4	352477	215035	0	0
T5	0	667256	0	0
T6	101372	605151	0	0
T12	226917	156011	0	0
T15	0	93814	0	0
T16	4958	0	0	0
T26	0	49911	0	0
T27	0	170816	0	0
T38	19134	14683	0	0
T39	19055	14583	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KeyLengthStableWhenValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	291077141	0	0
T2	400886	269523	0	0
T3	3181	0	0	0
T4	352477	215035	0	0
T5	0	667256	0	0
T6	101372	605151	0	0
T12	226917	156011	0	0
T15	0	93814	0	0
T16	4958	0	0	0
T26	0	49911	0	0
T27	0	170816	0	0
T38	19134	14683	0	0
T39	19055	14583	0	0
T40	147488	0	0	0
T41	851363	0	0	0

KmacEnStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	20644	0	0
T2	400886	13	0	0
T3	3181	0	0	0
T4	352477	163	0	0
T5	0	60	0	0
T6	101372	9	0	0
T12	226917	70	0	0
T15	0	20	0	0
T16	4958	2	0	0
T27	0	31	0	0
T38	19134	1	0	0
T39	19055	1	0	0
T40	147488	0	0	0
T41	851363	0	0	0

MaxKeyLenMatchToKey512_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0

ModeStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	31851	0	0
T2	400886	13	0	0
T3	3181	1	0	0
T4	352477	248	0	0
T6	101372	10	0	0
T12	226917	70	0	0
T15	0	54	0	0
T16	4958	3	0	0
T27	0	32	0	0
T38	19134	1	0	0
T39	19055	1	0	0
T40	147488	0	0	0
T41	851363	0	0	0

ProcessLatchedCleared_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	2	0	0
T109	89328	1	0	0
T110	0	1	0	0
T111	391268	0	0	0
T112	397697	0	0	0
T113	128265	0	0	0
T114	1434	0	0	0
T115	623837	0	0	0
T116	1148	0	0	0
T117	333733	0	0	0
T118	617586	0	0	0
T119	22839	0	0	0

StrengthStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	38063	0	0
T1	476048	2	0	0
T2	400886	18	0	0
T3	3181	2	0	0
T4	352477	270	0	0
T6	101372	8	0	0
T12	226917	97	0	0
T16	4958	2	0	0
T38	19134	2	0	0
T39	19055	2	0	0
T40	147488	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514977704	1514786187	0	0
T1	476048	476038	0	0
T2	400886	400824	0	0
T3	3181	3021	0	0
T4	352477	352376	0	0
T6	101372	101362	0	0
T12	226917	226911	0	0
T16	4958	4907	0	0
T38	19134	19072	0	0
T39	19055	18975	0	0
T40	147488	147481	0	0