Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1516181502	111343	0	0
entropy_period_rd_A	1516181502	1640	0	0
intr_enable_rd_A	1516181502	2130	0	0
prefix_0_rd_A	1516181502	1411	0	0
prefix_10_rd_A	1516181502	1512	0	0
prefix_1_rd_A	1516181502	1489	0	0
prefix_2_rd_A	1516181502	1328	0	0
prefix_3_rd_A	1516181502	1483	0	0
prefix_4_rd_A	1516181502	1358	0	0
prefix_5_rd_A	1516181502	1382	0	0
prefix_6_rd_A	1516181502	1396	0	0
prefix_7_rd_A	1516181502	1437	0	0
prefix_8_rd_A	1516181502	1301	0	0
prefix_9_rd_A	1516181502	1508	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	111343	0	0
T32	211588	17666	0	0
T68	0	15028	0	0
T69	0	35517	0	0
T70	0	34091	0	0
T74	3581	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T142	0	6430	0	0
T144	0	1	0	0
T145	0	120	0	0
T146	0	9	0	0
T147	398995	0	0	0
T148	127519	0	0	0
T149	601650	0	0	0
T150	157310	0	0	0
T151	2222	0	0	0
T152	21258	0	0	0
T153	528045	0	0	0
T154	84780	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1640	0	0
T95	5326	2	0	0
T97	6043	44	0	0
T98	2454	2	0	0
T135	22392	100	0	0
T136	24076	135	0	0
T144	5254	10	0	0
T163	12125	46	0	0
T164	2964	6	0	0
T165	26735	187	0	0
T166	4915	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	2130	0	0
T95	5326	3	0	0
T97	6043	29	0	0
T135	22392	175	0	0
T136	24076	98	0	0
T144	5254	9	0	0
T163	12125	20	0	0
T164	2964	14	0	0
T165	26735	175	0	0
T166	4915	8	0	0
T167	1275	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1411	0	0
T95	5326	3	0	0
T97	6043	30	0	0
T135	22392	81	0	0
T136	24076	90	0	0
T144	5254	3	0	0
T163	12125	11	0	0
T164	2964	12	0	0
T165	26735	180	0	0
T166	4915	9	0	0
T168	7583	14	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1512	0	0
T95	5326	3	0	0
T97	6043	30	0	0
T135	22392	71	0	0
T136	24076	79	0	0
T163	12125	68	0	0
T164	2964	3	0	0
T165	26735	233	0	0
T166	4915	9	0	0
T168	7583	13	0	0
T169	7426	17	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1489	0	0
T95	5326	13	0	0
T97	6043	32	0	0
T98	2454	5	0	0
T135	22392	87	0	0
T136	24076	71	0	0
T163	12125	60	0	0
T164	2964	9	0	0
T165	26735	224	0	0
T166	4915	8	0	0
T168	7583	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1328	0	0
T95	5326	9	0	0
T97	6043	19	0	0
T135	22392	101	0	0
T136	24076	93	0	0
T144	5254	7	0	0
T163	12125	36	0	0
T164	2964	9	0	0
T165	26735	206	0	0
T166	4915	3	0	0
T168	7583	26	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1483	0	0
T95	5326	6	0	0
T97	6043	21	0	0
T98	2454	1	0	0
T135	22392	92	0	0
T136	24076	71	0	0
T163	12125	45	0	0
T164	2964	7	0	0
T165	26735	236	0	0
T166	4915	14	0	0
T168	7583	22	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1358	0	0
T95	5326	6	0	0
T97	6043	25	0	0
T135	22392	75	0	0
T136	24076	71	0	0
T144	5254	8	0	0
T163	12125	15	0	0
T164	2964	9	0	0
T165	26735	235	0	0
T166	4915	12	0	0
T168	7583	17	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1382	0	0
T95	5326	7	0	0
T97	6043	20	0	0
T98	2454	5	0	0
T135	22392	104	0	0
T136	24076	72	0	0
T144	5254	12	0	0
T163	12125	34	0	0
T164	2964	12	0	0
T165	26735	182	0	0
T166	4915	16	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1396	0	0
T95	5326	6	0	0
T97	6043	23	0	0
T98	2454	4	0	0
T135	22392	87	0	0
T136	24076	72	0	0
T144	5254	5	0	0
T163	12125	53	0	0
T164	2964	7	0	0
T165	26735	199	0	0
T166	4915	13	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1437	0	0
T95	5326	4	0	0
T97	6043	24	0	0
T98	2454	1	0	0
T135	22392	84	0	0
T136	24076	65	0	0
T144	5254	2	0	0
T163	12125	65	0	0
T164	2964	11	0	0
T165	26735	209	0	0
T166	4915	9	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1301	0	0
T95	5326	6	0	0
T97	6043	16	0	0
T98	2454	9	0	0
T135	22392	60	0	0
T136	24076	81	0	0
T144	5254	7	0	0
T163	12125	26	0	0
T164	2964	5	0	0
T165	26735	178	0	0
T166	4915	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516181502	1508	0	0
T97	6043	13	0	0
T98	2454	2	0	0
T135	22392	102	0	0
T136	24076	67	0	0
T144	5254	2	0	0
T163	12125	23	0	0
T164	2964	10	0	0
T165	26735	241	0	0
T166	4915	11	0	0
T168	7583	13	0	0