Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	164481653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121069616

1

T1

323272

T2

326768

T3

162

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	148799296	1			T1	431877		T2	427019		T3	90
values[0x0]	65798625	1			T1	205084		T2	204346		T3	36
values[0x1]	70953348	1			T1	224014		T2	222159		T3	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127682364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157868905

1

T1

442293

T2

442507

T3

165

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	858906	1			T1	3407		T2	3023		T17	4
valid_sources[0x01]	1000186	1			T1	3305		T2	3200		T17	2
valid_sources[0x02]	933264	1			T1	3348		T2	3230		T17	4
valid_sources[0x03]	858554	1			T1	3583		T2	3286		T17	2
valid_sources[0x04]	1069819	1			T1	3277		T2	3257		T17	3
valid_sources[0x05]	858124	1			T1	3165		T2	3528		T17	7
valid_sources[0x06]	856046	1			T1	3458		T2	3190		T17	3
valid_sources[0x07]	1496807	1			T1	3333		T2	3533		T17	1
valid_sources[0x08]	862372	1			T1	3429		T2	3284		T17	3
valid_sources[0x09]	3174189	1			T1	3398		T2	3758		T17	4
valid_sources[0x0a]	1459510	1			T1	3381		T2	3639		T17	5
valid_sources[0x0b]	865580	1			T1	3284		T2	3637		T17	4
valid_sources[0x0c]	858844	1			T1	3473		T2	3465		T17	5
valid_sources[0x0d]	857717	1			T1	3337		T2	3290		T17	1
valid_sources[0x0e]	857965	1			T1	3226		T2	3575		T20	189
valid_sources[0x0f]	857477	1			T1	3392		T2	3255		T17	3
valid_sources[0x10]	855898	1			T1	3440		T2	3314		T17	4
valid_sources[0x11]	859944	1			T1	3155		T2	3266		T17	4
valid_sources[0x12]	865708	1			T1	3220		T2	3317		T17	5
valid_sources[0x13]	855356	1			T1	3211		T2	3554		T17	5
valid_sources[0x14]	3192862	1			T1	3217		T2	3457		T17	5
valid_sources[0x15]	857205	1			T1	3470		T2	3154		T17	4
valid_sources[0x16]	859003	1			T1	3353		T2	3233		T17	2
valid_sources[0x17]	859406	1			T1	3334		T2	3398		T17	4
valid_sources[0x18]	1042527	1			T1	3446		T2	3256		T17	1
valid_sources[0x19]	863009	1			T1	3343		T2	3391		T17	7
valid_sources[0x1a]	858340	1			T1	3426		T2	3126		T17	4
valid_sources[0x1b]	876805	1			T1	3365		T2	3129		T17	3
valid_sources[0x1c]	856329	1			T1	3363		T2	3550		T17	6
valid_sources[0x1d]	857835	1			T1	3244		T2	3276		T17	4
valid_sources[0x1e]	854948	1			T1	3484		T2	3749		T17	5
valid_sources[0x1f]	859201	1			T1	3366		T2	3343		T17	3
valid_sources[0x20]	855109	1			T1	3346		T2	3050		T17	10
valid_sources[0x21]	987762	1			T1	3128		T2	3349		T17	4
valid_sources[0x22]	1332020	1			T1	3257		T2	3247		T17	3
valid_sources[0x23]	2814080	1			T1	3265		T2	3264		T17	6
valid_sources[0x24]	869906	1			T1	3582		T2	3290		T17	5
valid_sources[0x25]	862153	1			T1	3357		T2	3429		T20	171
valid_sources[0x26]	858321	1			T1	3364		T2	3269		T17	4
valid_sources[0x27]	855359	1			T1	3215		T2	3322		T17	6
valid_sources[0x28]	876097	1			T1	3150		T2	3513		T17	5
valid_sources[0x29]	2184668	1			T1	3454		T2	3429		T17	1
valid_sources[0x2a]	1603813	1			T1	3264		T2	3328		T17	6
valid_sources[0x2b]	859601	1			T1	3287		T2	3234		T17	3
valid_sources[0x2c]	861184	1			T1	3479		T2	3368		T17	2
valid_sources[0x2d]	862349	1			T1	3336		T2	3641		T17	1
valid_sources[0x2e]	859890	1			T1	3330		T2	3375		T17	3
valid_sources[0x2f]	857636	1			T1	3355		T2	3105		T17	3
valid_sources[0x30]	864023	1			T1	3269		T2	3154		T17	6
valid_sources[0x31]	856395	1			T1	3312		T2	3192		T17	1
valid_sources[0x32]	856280	1			T1	3353		T2	3583		T17	3
valid_sources[0x33]	871241	1			T1	3369		T2	3349		T17	1
valid_sources[0x34]	862914	1			T1	3400		T2	3299		T3	91
valid_sources[0x35]	856433	1			T1	3431		T2	3217		T17	5
valid_sources[0x36]	1883167	1			T1	3375		T2	3370		T17	6
valid_sources[0x37]	855351	1			T1	3428		T2	3283		T17	3
valid_sources[0x38]	3192132	1			T1	3521		T2	3312		T17	2
valid_sources[0x39]	857480	1			T1	3199		T2	3500		T17	2
valid_sources[0x3a]	1493633	1			T1	3396		T2	3587		T17	4
valid_sources[0x3b]	853136	1			T1	3381		T2	3192		T17	3
valid_sources[0x3c]	948467	1			T1	3428		T2	3549		T17	3
valid_sources[0x3d]	861211	1			T1	3383		T2	3376		T17	3
valid_sources[0x3e]	857133	1			T1	3208		T2	3468		T17	3
valid_sources[0x3f]	855931	1			T1	3315		T2	3361		T17	4
valid_sources[0x40]	855768	1			T1	3413		T2	3097		T17	3
valid_sources[0x41]	894528	1			T1	3239		T2	3276		T17	3
valid_sources[0x42]	860151	1			T1	3297		T2	3374		T17	3
valid_sources[0x43]	1749083	1			T1	3455		T2	3433		T17	6
valid_sources[0x44]	860339	1			T1	3235		T2	3613		T17	2
valid_sources[0x45]	996574	1			T1	3467		T2	3468		T17	6
valid_sources[0x46]	1039569	1			T1	3347		T2	3608		T17	3
valid_sources[0x47]	856886	1			T1	3221		T2	3086		T17	6
valid_sources[0x48]	853936	1			T1	3350		T2	3305		T17	5
valid_sources[0x49]	1255195	1			T1	3396		T2	3380		T17	2
valid_sources[0x4a]	1066743	1			T1	3255		T2	3286		T17	6
valid_sources[0x4b]	856751	1			T1	3358		T2	3544		T17	5
valid_sources[0x4c]	1319240	1			T1	3329		T2	3118		T17	4
valid_sources[0x4d]	960777	1			T1	3423		T2	3287		T17	4
valid_sources[0x4e]	859777	1			T1	3374		T2	3262		T17	1
valid_sources[0x4f]	858764	1			T1	3397		T2	3465		T17	4
valid_sources[0x50]	860261	1			T1	3305		T2	3280		T17	3
valid_sources[0x51]	1707980	1			T1	3441		T2	3208		T17	3
valid_sources[0x52]	872845	1			T1	3372		T2	3494		T17	11148
valid_sources[0x53]	857251	1			T1	3322		T2	3458		T17	1
valid_sources[0x54]	855676	1			T1	3448		T2	3429		T17	3
valid_sources[0x55]	855211	1			T1	3235		T2	3459		T17	2
valid_sources[0x56]	1033747	1			T1	3603		T2	3262		T17	2
valid_sources[0x57]	1020229	1			T1	3338		T2	3183		T17	1
valid_sources[0x58]	954948	1			T1	3281		T2	3347		T20	227
valid_sources[0x59]	1001294	1			T1	3351		T2	3470		T20	185
valid_sources[0x5a]	905927	1			T1	3441		T2	3485		T17	2
valid_sources[0x5b]	862230	1			T1	3278		T2	3316		T17	8
valid_sources[0x5c]	1492906	1			T1	3371		T2	3462		T17	5
valid_sources[0x5d]	853654	1			T1	3555		T2	3473		T17	2
valid_sources[0x5e]	864688	1			T1	3125		T2	3048		T17	1
valid_sources[0x5f]	855713	1			T1	3312		T2	3377		T17	3
valid_sources[0x60]	870641	1			T1	3421		T2	3612		T17	3
valid_sources[0x61]	858279	1			T1	3295		T2	3734		T17	4
valid_sources[0x62]	854055	1			T1	3229		T2	3270		T17	4
valid_sources[0x63]	857799	1			T1	3475		T2	3163		T17	1
valid_sources[0x64]	4138891	1			T1	3365		T2	3585		T17	2
valid_sources[0x65]	859415	1			T1	3519		T2	3162		T17	3
valid_sources[0x66]	1716917	1			T1	3361		T2	3367		T17	5
valid_sources[0x67]	854467	1			T1	3362		T2	3381		T17	8
valid_sources[0x68]	970348	1			T1	3413		T2	3338		T17	4
valid_sources[0x69]	859503	1			T1	3375		T2	3356		T17	3
valid_sources[0x6a]	859238	1			T1	3441		T2	3522		T17	3
valid_sources[0x6b]	858508	1			T1	3588		T2	3436		T17	3
valid_sources[0x6c]	854719	1			T1	3351		T2	3338		T17	1
valid_sources[0x6d]	1717606	1			T1	3310		T2	3161		T17	3
valid_sources[0x6e]	863747	1			T1	3250		T2	3119		T17	6
valid_sources[0x6f]	1037661	1			T1	3330		T2	3410		T17	1
valid_sources[0x70]	1069401	1			T1	3379		T2	2948		T17	8
valid_sources[0x71]	3340046	1			T1	3540		T2	3321		T17	1
valid_sources[0x72]	859166	1			T1	3385		T2	3319		T17	4
valid_sources[0x73]	1504839	1			T1	3431		T2	3494		T17	2
valid_sources[0x74]	858646	1			T1	3278		T2	3160		T17	3
valid_sources[0x75]	989733	1			T1	3179		T2	3773		T17	7
valid_sources[0x76]	3198246	1			T1	3346		T2	3540		T17	3
valid_sources[0x77]	906382	1			T1	3492		T2	3122		T17	2
valid_sources[0x78]	859603	1			T1	3525		T2	3391		T20	183
valid_sources[0x79]	855744	1			T1	3494		T2	3388		T17	2
valid_sources[0x7a]	864491	1			T1	3551		T2	3256		T17	2
valid_sources[0x7b]	1314322	1			T1	3417		T2	3344		T17	3
valid_sources[0x7c]	1055623	1			T1	3414		T2	3327		T17	4
valid_sources[0x7d]	980598	1			T1	3159		T2	3423		T17	2
valid_sources[0x7e]	871170	1			T1	3149		T2	3182		T17	2
valid_sources[0x7f]	875791	1			T1	3375		T2	3309		T17	1
valid_sources[0x80]	848916	1			T1	3471		T2	3243		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47113289

1

T1

112379

T2

111928

T3

86

values[0x0]

all_enables

biggest_size

39616173

1

T1

114396

T2

116245

T3

34

values[0x1]

all_enables

biggest_size

34340154

1

T1

96497

T2

98595

T3

42