Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

165267034

1

T1

537703

T2

526756

T3

12

full_word

121118550

1

T1

323272

T2

326768

T3

162

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	286385304	1			T1	860975		T2	853524		T3	174
auto[TlIntgErrCmd]	78	1			T121	4		T122	3		T123	6
auto[TlIntgErrData]	97	1			T121	3		T122	5		T123	6
auto[TlIntgErrBoth]	105	1			T121	3		T122	2		T123	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148982307

1

T1

431877

T2

427019

T3

90

auto[1]

137403277

1

T1

429098

T2

426505

T3

84

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	101854887	1			T1	319498		T2	315091		T3	4
auto[TlIntgErrNone]	partial	auto[1]	63411885	1			T1	218205		T2	211665		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	47127293	1			T1	112379		T2	111928		T3	86
auto[TlIntgErrNone]	full_word	auto[1]	73991239	1			T1	210893		T2	214840		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T121	1		T122	2		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T121	3		T122	1		T123	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T178	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T179	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T122	4		T123	2		T154	5
auto[TlIntgErrData]	partial	auto[1]	51	1			T121	2		T122	1		T123	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T121	1		T180	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T182	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T122	1		T123	4		T154	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T121	3		T122	1		T123	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T179	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T154	1		T183	1		T184	1