Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1412720223	200991	0	0
RunThenComplete_M	1412720223	2087750	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1412720223	200991	0	0
T1	627433	374	0	0
T2	797937	374	0	0
T3	5401	0	0	0
T7	70958	14	0	0
T17	129361	11	0	0
T20	359758	43	0	0
T34	236099	161	0	0
T35	683621	2337	0	0
T36	15218	9	0	0
T37	150614	194	0	0
T38	0	9	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1412720223	2087750	0	0
T1	627433	5526	0	0
T2	797937	5526	0	0
T3	5401	0	0	0
T7	70958	74	0	0
T17	129361	52	0	0
T20	359758	243	0	0
T34	236099	6363	0	0
T35	683621	13147	0	0
T36	15218	31	0	0
T37	150614	7442	0	0
T38	0	31	0	0