Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1414035321	139593	0	0
entropy_period_rd_A	1414035321	1929	0	0
intr_enable_rd_A	1414035321	2721	0	0
prefix_0_rd_A	1414035321	1965	0	0
prefix_10_rd_A	1414035321	1858	0	0
prefix_1_rd_A	1414035321	1986	0	0
prefix_2_rd_A	1414035321	1846	0	0
prefix_3_rd_A	1414035321	1837	0	0
prefix_4_rd_A	1414035321	2012	0	0
prefix_5_rd_A	1414035321	2049	0	0
prefix_6_rd_A	1414035321	1963	0	0
prefix_7_rd_A	1414035321	1862	0	0
prefix_8_rd_A	1414035321	1948	0	0
prefix_9_rd_A	1414035321	2013	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	139593	0	0
T26	0	87827	0	0
T56	235573	32242	0	0
T57	467078	0	0	0
T58	331368	0	0	0
T68	0	16541	0	0
T121	0	1	0	0
T122	0	1	0	0
T127	0	184	0	0
T128	0	106	0	0
T129	0	87	0	0
T130	0	138	0	0
T131	0	26	0	0
T134	609817	0	0	0
T135	703582	0	0	0
T136	581360	0	0	0
T137	445853	0	0	0
T138	121592	0	0	0
T139	523915	0	0	0
T140	4555	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1929	0	0
T95	3791	17	0	0
T98	4029	26	0	0
T102	3234	15	0	0
T121	12938	60	0	0
T152	3270	4	0	0
T153	10428	37	0	0
T154	26835	127	0	0
T155	6360	18	0	0
T156	2357	4	0	0
T157	2929	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	2721	0	0
T102	3234	5	0	0
T121	12938	84	0	0
T133	13862	7	0	0
T152	3270	19	0	0
T153	10428	39	0	0
T154	26835	177	0	0
T158	1436	9	0	0
T159	923	11	0	0
T160	1632	10	0	0
T161	1650	18	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1965	0	0
T95	3791	8	0	0
T98	4029	26	0	0
T102	3234	21	0	0
T121	12938	53	0	0
T152	3270	2	0	0
T153	10428	31	0	0
T154	26835	73	0	0
T155	6360	27	0	0
T156	2357	5	0	0
T157	2929	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1858	0	0
T95	3791	13	0	0
T102	3234	10	0	0
T121	12938	43	0	0
T133	13862	1	0	0
T152	3270	10	0	0
T153	10428	26	0	0
T154	26835	87	0	0
T155	6360	25	0	0
T156	2357	11	0	0
T157	2929	13	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1986	0	0
T95	3791	13	0	0
T98	4029	20	0	0
T102	3234	3	0	0
T121	12938	38	0	0
T152	3270	7	0	0
T153	10428	46	0	0
T154	26835	89	0	0
T155	6360	28	0	0
T156	2357	2	0	0
T157	2929	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1846	0	0
T95	3791	21	0	0
T98	4029	10	0	0
T102	3234	8	0	0
T121	12938	24	0	0
T152	3270	9	0	0
T153	10428	32	0	0
T154	26835	97	0	0
T155	6360	19	0	0
T156	2357	9	0	0
T157	2929	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1837	0	0
T95	3791	16	0	0
T98	4029	16	0	0
T102	3234	10	0	0
T121	12938	39	0	0
T153	10428	39	0	0
T154	26835	68	0	0
T155	6360	21	0	0
T157	2929	11	0	0
T162	3447	3	0	0
T163	9697	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	2012	0	0
T95	3791	16	0	0
T98	4029	19	0	0
T102	3234	14	0	0
T121	12938	58	0	0
T152	3270	7	0	0
T153	10428	74	0	0
T154	26835	79	0	0
T155	6360	20	0	0
T157	2929	12	0	0
T162	3447	12	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	2049	0	0
T95	3791	13	0	0
T98	4029	16	0	0
T102	3234	9	0	0
T121	12938	36	0	0
T152	3270	10	0	0
T153	10428	44	0	0
T154	26835	77	0	0
T155	6360	18	0	0
T156	2357	6	0	0
T157	2929	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1963	0	0
T95	3791	6	0	0
T98	4029	18	0	0
T102	3234	24	0	0
T121	12938	38	0	0
T152	3270	11	0	0
T153	10428	31	0	0
T154	26835	77	0	0
T155	6360	18	0	0
T157	2929	10	0	0
T162	3447	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1862	0	0
T95	3791	11	0	0
T98	4029	13	0	0
T102	3234	10	0	0
T121	12938	29	0	0
T152	3270	12	0	0
T153	10428	21	0	0
T154	26835	64	0	0
T155	6360	8	0	0
T156	2357	6	0	0
T157	2929	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	1948	0	0
T95	3791	13	0	0
T98	4029	14	0	0
T102	3234	14	0	0
T121	12938	34	0	0
T153	10428	12	0	0
T154	26835	99	0	0
T155	6360	16	0	0
T156	2357	14	0	0
T157	2929	15	0	0
T162	3447	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1414035321	2013	0	0
T95	3791	15	0	0
T98	4029	16	0	0
T102	3234	12	0	0
T121	12938	50	0	0
T152	3270	2	0	0
T153	10428	26	0	0
T154	26835	84	0	0
T155	6360	14	0	0
T156	2357	3	0	0
T157	2929	13	0	0