Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167373949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124030017

1

T1

188782

T2

7

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	151966975	1			T1	238051		T2	1		T3	13
values[0x0]	67083276	1			T1	82665		T2	5		T3	17
values[0x1]	72353715	1			T1	87398		T2	11		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129922164	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161481802

1

T1

242051

T2

10

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1795980	1			T1	1611		T7	182		T16	147
valid_sources[0x01]	927494	1			T1	1632		T7	169		T16	95
valid_sources[0x02]	1207826	1			T1	1625		T7	171		T16	88
valid_sources[0x03]	1097509	1			T1	1614		T7	173		T16	146
valid_sources[0x04]	963041	1			T1	1561		T3	1		T7	175
valid_sources[0x05]	1103997	1			T1	1588		T3	1		T7	179
valid_sources[0x06]	1083451	1			T1	1499		T3	1		T7	170
valid_sources[0x07]	928833	1			T1	1577		T7	164		T16	128
valid_sources[0x08]	1579575	1			T1	1538		T7	199		T16	99
valid_sources[0x09]	933210	1			T1	1583		T7	165		T16	122
valid_sources[0x0a]	1233708	1			T1	1559		T7	190		T16	100
valid_sources[0x0b]	937594	1			T1	1466		T7	165		T16	96
valid_sources[0x0c]	935925	1			T1	1590		T7	183		T16	98
valid_sources[0x0d]	1377570	1			T1	1503		T7	166		T16	77
valid_sources[0x0e]	936591	1			T1	1658		T3	1		T7	169
valid_sources[0x0f]	936343	1			T1	1559		T7	181		T16	142
valid_sources[0x10]	933158	1			T1	1576		T7	178		T16	127
valid_sources[0x11]	941067	1			T1	1730		T7	196		T16	130
valid_sources[0x12]	988599	1			T1	1540		T7	191		T16	123
valid_sources[0x13]	936866	1			T1	1555		T7	166		T16	103
valid_sources[0x14]	1787494	1			T1	1640		T7	174		T16	145
valid_sources[0x15]	937450	1			T1	1594		T7	204		T16	109
valid_sources[0x16]	2686523	1			T1	1771		T7	175		T16	159
valid_sources[0x17]	932141	1			T1	1586		T7	196		T16	128
valid_sources[0x18]	961000	1			T1	1634		T7	196		T16	157
valid_sources[0x19]	1775348	1			T1	1628		T7	157		T16	101
valid_sources[0x1a]	1883506	1			T1	1585		T7	159		T16	99
valid_sources[0x1b]	1294889	1			T1	1625		T3	1		T7	171
valid_sources[0x1c]	1111360	1			T1	1579		T7	190		T16	172
valid_sources[0x1d]	933625	1			T1	1570		T7	206		T16	113
valid_sources[0x1e]	942991	1			T1	1558		T7	185		T16	114
valid_sources[0x1f]	936345	1			T1	1526		T7	169		T16	73
valid_sources[0x20]	929251	1			T1	1617		T7	207		T16	136
valid_sources[0x21]	932674	1			T1	1472		T7	173		T16	127
valid_sources[0x22]	938194	1			T1	1613		T7	170		T16	151
valid_sources[0x23]	932748	1			T1	1621		T3	1		T7	191
valid_sources[0x24]	994239	1			T1	1528		T7	184		T16	102
valid_sources[0x25]	933751	1			T1	1597		T7	211		T16	146
valid_sources[0x26]	932596	1			T1	1652		T7	163		T16	130
valid_sources[0x27]	1861485	1			T1	1670		T3	1		T7	154
valid_sources[0x28]	933173	1			T1	1663		T7	169		T16	97
valid_sources[0x29]	940064	1			T1	1605		T7	199		T16	123
valid_sources[0x2a]	1523609	1			T1	1576		T7	187		T16	122
valid_sources[0x2b]	936080	1			T1	1653		T7	183		T16	84
valid_sources[0x2c]	929806	1			T1	1549		T7	187		T16	97
valid_sources[0x2d]	1790586	1			T1	1638		T3	1		T7	182
valid_sources[0x2e]	1386089	1			T1	1606		T7	181		T16	112
valid_sources[0x2f]	938137	1			T1	1637		T7	160		T16	77
valid_sources[0x30]	933153	1			T1	1605		T7	186		T16	163
valid_sources[0x31]	937577	1			T1	1575		T7	172		T16	122
valid_sources[0x32]	933577	1			T1	1515		T7	172		T16	97
valid_sources[0x33]	934028	1			T1	1659		T7	168		T16	120
valid_sources[0x34]	942339	1			T1	1577		T3	1		T7	177
valid_sources[0x35]	937365	1			T1	1580		T7	193		T16	113
valid_sources[0x36]	934674	1			T1	1601		T7	186		T16	98
valid_sources[0x37]	1780839	1			T1	1588		T7	187		T16	121
valid_sources[0x38]	1079363	1			T1	1659		T7	198		T16	91
valid_sources[0x39]	968051	1			T1	1597		T7	167		T16	118
valid_sources[0x3a]	1587959	1			T1	1576		T7	168		T16	126
valid_sources[0x3b]	2136974	1			T1	1552		T7	194		T16	143
valid_sources[0x3c]	1347828	1			T1	1536		T7	193		T16	93
valid_sources[0x3d]	1393383	1			T1	1515		T7	172		T16	124
valid_sources[0x3e]	938321	1			T1	1539		T7	142		T16	94
valid_sources[0x3f]	1397782	1			T1	1494		T7	178		T16	128
valid_sources[0x40]	951282	1			T1	1611		T3	1		T7	175
valid_sources[0x41]	935656	1			T1	1569		T3	1		T7	192
valid_sources[0x42]	936999	1			T1	1571		T7	161		T16	109
valid_sources[0x43]	935126	1			T1	1537		T7	193		T16	131
valid_sources[0x44]	937347	1			T1	1580		T7	184		T16	99
valid_sources[0x45]	1113406	1			T1	1584		T7	188		T16	165
valid_sources[0x46]	937847	1			T1	1650		T7	177		T16	129
valid_sources[0x47]	934276	1			T1	1612		T7	187		T16	92
valid_sources[0x48]	1427730	1			T1	1595		T7	172		T16	101
valid_sources[0x49]	1072056	1			T1	1596		T7	205		T16	144
valid_sources[0x4a]	1120735	1			T1	1510		T3	1		T7	173
valid_sources[0x4b]	932494	1			T1	1577		T7	184		T16	82
valid_sources[0x4c]	938709	1			T1	1471		T7	164		T16	116
valid_sources[0x4d]	935101	1			T1	1750		T3	1		T7	168
valid_sources[0x4e]	936149	1			T1	1610		T7	162		T16	99
valid_sources[0x4f]	937552	1			T1	1573		T7	217		T16	103
valid_sources[0x50]	935989	1			T1	1509		T7	169		T16	112
valid_sources[0x51]	937609	1			T1	1720		T7	168		T16	123
valid_sources[0x52]	1290186	1			T1	1631		T7	180		T16	130
valid_sources[0x53]	956128	1			T1	1524		T7	190		T16	95
valid_sources[0x54]	935967	1			T1	1663		T7	173		T16	107
valid_sources[0x55]	937797	1			T1	1577		T3	1		T7	185
valid_sources[0x56]	1032656	1			T1	1607		T7	190		T16	146
valid_sources[0x57]	943780	1			T1	1562		T7	190		T16	74
valid_sources[0x58]	1772108	1			T1	1637		T7	174		T16	162
valid_sources[0x59]	1105622	1			T1	1569		T7	192		T16	119
valid_sources[0x5a]	934601	1			T1	1650		T7	184		T16	94
valid_sources[0x5b]	942943	1			T1	1628		T3	1		T7	160
valid_sources[0x5c]	1789920	1			T1	1674		T3	1		T7	195
valid_sources[0x5d]	1819655	1			T1	1596		T7	175		T16	138
valid_sources[0x5e]	934030	1			T1	1561		T7	191		T16	205
valid_sources[0x5f]	934318	1			T1	1580		T7	183		T16	102
valid_sources[0x60]	941838	1			T1	1575		T3	1		T7	174
valid_sources[0x61]	956687	1			T1	1580		T7	190		T16	125
valid_sources[0x62]	935495	1			T1	1563		T7	175		T16	144
valid_sources[0x63]	1835121	1			T1	1532		T7	176		T16	106
valid_sources[0x64]	934287	1			T1	1584		T7	176		T16	119
valid_sources[0x65]	933493	1			T1	1554		T7	178		T16	104
valid_sources[0x66]	1144554	1			T1	1541		T7	161		T16	126
valid_sources[0x67]	928093	1			T1	1601		T3	1		T7	180
valid_sources[0x68]	1687930	1			T1	1584		T3	1		T7	180
valid_sources[0x69]	931351	1			T1	1518		T7	178		T16	123
valid_sources[0x6a]	1181908	1			T1	1593		T7	185		T16	208
valid_sources[0x6b]	934391	1			T1	1658		T7	181		T16	111
valid_sources[0x6c]	1021788	1			T1	1637		T7	171		T16	125
valid_sources[0x6d]	1011855	1			T1	1641		T7	202		T16	77
valid_sources[0x6e]	934423	1			T1	1689		T7	179		T16	69
valid_sources[0x6f]	936638	1			T1	1558		T7	186		T16	110
valid_sources[0x70]	935147	1			T1	1672		T7	173		T16	174
valid_sources[0x71]	935694	1			T1	1708		T3	2		T7	198
valid_sources[0x72]	936631	1			T1	1590		T7	196		T16	121
valid_sources[0x73]	938098	1			T1	1699		T7	163		T16	124
valid_sources[0x74]	1204629	1			T1	1535		T2	1		T7	195
valid_sources[0x75]	1590906	1			T1	1711		T3	1		T7	176
valid_sources[0x76]	961027	1			T1	1669		T7	181		T16	112
valid_sources[0x77]	932569	1			T1	1656		T7	181		T16	143
valid_sources[0x78]	960810	1			T1	1655		T2	1		T7	183
valid_sources[0x79]	938636	1			T1	1715		T3	1		T7	176
valid_sources[0x7a]	932800	1			T1	1635		T7	182		T16	134
valid_sources[0x7b]	941188	1			T1	1546		T7	173		T16	129
valid_sources[0x7c]	2629308	1			T1	1445		T7	165		T16	136
valid_sources[0x7d]	937063	1			T1	1602		T7	190		T16	115
valid_sources[0x7e]	929978	1			T1	1600		T7	177		T16	98
valid_sources[0x7f]	958656	1			T1	1560		T7	183		T16	106
valid_sources[0x80]	935187	1			T1	1611		T7	166		T16	97

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48269955

1

T1

73029

T2

1

T3

9

values[0x0]

all_enables

biggest_size

40540526

1

T1

60233

T2

3

T3

10

values[0x1]

all_enables

biggest_size

35219536

1

T1

55520

T2

3

T3

9