Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

168649097

1

T1

219332

T2

10

T3

16

full_word

124109545

1

T1

188782

T2

7

T3

28

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	292758342	1			T1	408114		T2	17		T3	44
auto[TlIntgErrCmd]	98	1			T126	4		T127	3		T128	7
auto[TlIntgErrData]	90	1			T126	2		T127	5		T128	6
auto[TlIntgErrBoth]	112	1			T126	4		T127	2		T128	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152266939

1

T1

238051

T2

1

T3

13

auto[1]

140491703

1

T1

170063

T2

16

T3

31

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	103973846	1			T1	165022		T3	4		T7	148487
auto[TlIntgErrNone]	partial	auto[1]	64674980	1			T1	54310		T2	10		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	48292946	1			T1	73029		T2	1		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	75816570	1			T1	115753		T2	6		T3	19
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T126	3		T127	3		T128	5
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T126	1		T128	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T173	1		T174	1		T175	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T128	1		T176	1		T172	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T126	1		T127	2		T128	4
auto[TlIntgErrData]	partial	auto[1]	35	1			T126	1		T127	2		T128	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T171	1		T172	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T127	1		T161	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T127	1		T128	2		T161	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T126	4		T128	4		T161	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T178	1		T172	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T127	1		T128	1		T175	1