Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1454008736	207178	0	0
RunThenComplete_M	1454008736	2138683	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1454008736	207178	0	0
T1	101404	211	0	0
T2	1037	0	0	0
T3	1635	0	0	0
T7	531627	344	0	0
T8	312546	108	0	0
T11	3504	0	0	0
T16	323417	29	0	0
T34	493660	76	0	0
T35	24201	9	0	0
T36	90866	89	0	0
T54	0	310	0	0
T55	0	390	0	0
T56	0	16	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1454008736	2138683	0	0
T1	101404	3170	0	0
T2	1037	0	0	0
T3	1635	0	0	0
T7	531627	3087	0	0
T8	312546	2043	0	0
T11	3504	0	0	0
T16	323417	158	0	0
T34	493660	2044	0	0
T35	24201	31	0	0
T36	90866	231	0	0
T54	0	5462	0	0
T55	0	5542	0	0
T56	0	89	0	0