Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1455538489	224755	0	0
entropy_period_rd_A	1455538489	2597	0	0
intr_enable_rd_A	1455538489	3685	0	0
prefix_0_rd_A	1455538489	2934	0	0
prefix_10_rd_A	1455538489	2777	0	0
prefix_1_rd_A	1455538489	2728	0	0
prefix_2_rd_A	1455538489	2736	0	0
prefix_3_rd_A	1455538489	2659	0	0
prefix_4_rd_A	1455538489	2768	0	0
prefix_5_rd_A	1455538489	2745	0	0
prefix_6_rd_A	1455538489	2829	0	0
prefix_7_rd_A	1455538489	2844	0	0
prefix_8_rd_A	1455538489	2915	0	0
prefix_9_rd_A	1455538489	2980	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	224755	0	0
T24	0	26123	0	0
T42	203767	16412	0	0
T43	0	74980	0	0
T59	261349	0	0	0
T126	0	1	0	0
T133	0	103667	0	0
T134	0	56	0	0
T135	0	138	0	0
T136	0	186	0	0
T138	0	3	0	0
T139	460121	0	0	0
T140	731461	0	0	0
T141	117000	0	0	0
T142	628201	0	0	0
T143	107995	0	0	0
T144	167497	0	0	0
T145	19601	0	0	0
T146	959258	0	0	0
T147	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2597	0	0
T102	5448	25	0	0
T104	4950	13	0	0
T107	13191	55	0	0
T112	4974	12	0	0
T138	8782	21	0	0
T157	2976	13	0	0
T158	8385	19	0	0
T159	1882	2	0	0
T160	6941	7	0	0
T161	21013	71	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	3685	0	0
T102	5448	48	0	0
T104	4950	18	0	0
T107	13191	65	0	0
T112	4974	42	0	0
T129	1542	26	0	0
T138	8782	28	0	0
T157	2976	6	0	0
T158	8385	9	0	0
T162	1833	25	0	0
T163	1261	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2934	0	0
T102	5448	17	0	0
T104	4950	19	0	0
T107	13191	64	0	0
T112	4974	15	0	0
T138	8782	12	0	0
T157	2976	6	0	0
T158	8385	21	0	0
T159	1882	6	0	0
T160	6941	35	0	0
T161	21013	41	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2777	0	0
T102	5448	7	0	0
T104	4950	25	0	0
T107	13191	49	0	0
T112	4974	36	0	0
T138	8782	21	0	0
T157	2976	6	0	0
T158	8385	21	0	0
T159	1882	3	0	0
T160	6941	13	0	0
T161	21013	41	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2728	0	0
T102	5448	5	0	0
T104	4950	8	0	0
T107	13191	47	0	0
T112	4974	17	0	0
T138	8782	15	0	0
T157	2976	11	0	0
T158	8385	14	0	0
T159	1882	5	0	0
T160	6941	20	0	0
T161	21013	47	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2736	0	0
T102	5448	25	0	0
T104	4950	14	0	0
T107	13191	48	0	0
T112	4974	13	0	0
T138	8782	15	0	0
T157	2976	9	0	0
T158	8385	21	0	0
T159	1882	5	0	0
T160	6941	22	0	0
T161	21013	40	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2659	0	0
T102	5448	30	0	0
T104	4950	18	0	0
T107	13191	49	0	0
T112	4974	21	0	0
T138	8782	10	0	0
T157	2976	11	0	0
T158	8385	17	0	0
T159	1882	3	0	0
T160	6941	12	0	0
T161	21013	30	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2768	0	0
T102	5448	13	0	0
T104	4950	18	0	0
T107	13191	54	0	0
T112	4974	19	0	0
T138	8782	18	0	0
T157	2976	2	0	0
T158	8385	18	0	0
T159	1882	5	0	0
T160	6941	36	0	0
T161	21013	36	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2745	0	0
T102	5448	14	0	0
T104	4950	30	0	0
T107	13191	41	0	0
T112	4974	22	0	0
T138	8782	24	0	0
T157	2976	4	0	0
T158	8385	16	0	0
T159	1882	5	0	0
T160	6941	23	0	0
T161	21013	34	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2829	0	0
T102	5448	17	0	0
T104	4950	20	0	0
T107	13191	67	0	0
T112	4974	18	0	0
T138	8782	27	0	0
T157	2976	5	0	0
T158	8385	14	0	0
T159	1882	7	0	0
T160	6941	41	0	0
T161	21013	68	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2844	0	0
T102	5448	12	0	0
T104	4950	28	0	0
T107	13191	47	0	0
T112	4974	25	0	0
T138	8782	28	0	0
T157	2976	14	0	0
T158	8385	6	0	0
T159	1882	1	0	0
T160	6941	8	0	0
T161	21013	40	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2915	0	0
T102	5448	13	0	0
T104	4950	17	0	0
T107	13191	58	0	0
T112	4974	25	0	0
T138	8782	23	0	0
T157	2976	6	0	0
T158	8385	19	0	0
T159	1882	4	0	0
T160	6941	11	0	0
T161	21013	67	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455538489	2980	0	0
T102	5448	32	0	0
T104	4950	11	0	0
T107	13191	64	0	0
T112	4974	20	0	0
T138	8782	11	0	0
T157	2976	3	0	0
T158	8385	23	0	0
T159	1882	1	0	0
T160	6941	6	0	0
T161	21013	40	0	0