Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146972 |
1 |
|
|
T7 |
433 |
|
T8 |
576 |
|
T19 |
115 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
74530 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
54713 |
1 |
|
|
T7 |
427 |
|
T8 |
570 |
|
T19 |
114 |
seven_bytes |
2581 |
1 |
|
|
T20 |
27 |
|
T21 |
52 |
|
T18 |
79 |
six_bytes |
2534 |
1 |
|
|
T20 |
21 |
|
T21 |
55 |
|
T18 |
81 |
five_bytes |
2475 |
1 |
|
|
T20 |
22 |
|
T21 |
40 |
|
T18 |
77 |
four_bytes |
2562 |
1 |
|
|
T20 |
27 |
|
T21 |
63 |
|
T18 |
64 |
three_bytes |
2529 |
1 |
|
|
T20 |
18 |
|
T21 |
51 |
|
T18 |
62 |
two_bytes |
2505 |
1 |
|
|
T20 |
23 |
|
T21 |
37 |
|
T18 |
77 |
one_byte |
2543 |
1 |
|
|
T20 |
21 |
|
T21 |
53 |
|
T18 |
61 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
144118 |
1 |
|
|
T7 |
421 |
|
T8 |
564 |
|
T19 |
113 |
auto[1] |
2854 |
1 |
|
|
T7 |
12 |
|
T8 |
12 |
|
T19 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146972 |
1 |
|
|
T7 |
433 |
|
T8 |
576 |
|
T19 |
115 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146962 |
1 |
|
|
T7 |
433 |
|
T8 |
576 |
|
T19 |
115 |
auto[1] |
10 |
1 |
|
|
T75 |
1 |
|
T190 |
1 |
|
T76 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1014 |
1 |
|
|
T7 |
6 |
|
T8 |
6 |
|
T19 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2854 |
1 |
|
|
T7 |
12 |
|
T8 |
12 |
|
T19 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
154129 |
1 |
|
|
T7 |
471 |
|
T8 |
12 |
|
T19 |
87 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
79659 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55491 |
1 |
|
|
T7 |
465 |
|
T8 |
11 |
|
T19 |
86 |
seven_bytes |
2731 |
1 |
|
|
T20 |
29 |
|
T21 |
62 |
|
T18 |
52 |
six_bytes |
2701 |
1 |
|
|
T20 |
22 |
|
T21 |
46 |
|
T18 |
56 |
five_bytes |
2697 |
1 |
|
|
T20 |
24 |
|
T21 |
63 |
|
T18 |
48 |
four_bytes |
2770 |
1 |
|
|
T20 |
30 |
|
T21 |
46 |
|
T18 |
49 |
three_bytes |
2691 |
1 |
|
|
T20 |
28 |
|
T21 |
53 |
|
T18 |
50 |
two_bytes |
2669 |
1 |
|
|
T20 |
25 |
|
T21 |
45 |
|
T18 |
55 |
one_byte |
2720 |
1 |
|
|
T20 |
25 |
|
T21 |
52 |
|
T18 |
52 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
151161 |
1 |
|
|
T7 |
459 |
|
T8 |
10 |
|
T19 |
85 |
auto[1] |
2968 |
1 |
|
|
T7 |
12 |
|
T8 |
2 |
|
T19 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
154129 |
1 |
|
|
T7 |
471 |
|
T8 |
12 |
|
T19 |
87 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
154119 |
1 |
|
|
T7 |
471 |
|
T8 |
12 |
|
T19 |
87 |
auto[1] |
10 |
1 |
|
|
T21 |
1 |
|
T9 |
1 |
|
T75 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1027 |
1 |
|
|
T7 |
6 |
|
T8 |
1 |
|
T19 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2968 |
1 |
|
|
T7 |
12 |
|
T8 |
2 |
|
T19 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
314844 |
1 |
|
|
T2 |
3 |
|
T6 |
112 |
|
T7 |
708 |
auto[1] |
495 |
1 |
|
|
T5 |
4 |
|
T9 |
78 |
|
T10 |
96 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
164732 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
111879 |
1 |
|
|
T2 |
3 |
|
T6 |
111 |
|
T7 |
694 |
seven_bytes |
5538 |
1 |
|
|
T20 |
89 |
|
T21 |
63 |
|
T18 |
159 |
six_bytes |
5494 |
1 |
|
|
T20 |
77 |
|
T21 |
44 |
|
T18 |
155 |
five_bytes |
5534 |
1 |
|
|
T20 |
86 |
|
T21 |
56 |
|
T18 |
148 |
four_bytes |
5547 |
1 |
|
|
T20 |
88 |
|
T21 |
63 |
|
T18 |
184 |
three_bytes |
5393 |
1 |
|
|
T20 |
68 |
|
T21 |
62 |
|
T18 |
150 |
two_bytes |
5660 |
1 |
|
|
T20 |
72 |
|
T21 |
68 |
|
T18 |
140 |
one_byte |
5562 |
1 |
|
|
T20 |
97 |
|
T21 |
49 |
|
T18 |
173 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309277 |
1 |
|
|
T2 |
3 |
|
T6 |
110 |
|
T7 |
680 |
auto[1] |
6062 |
1 |
|
|
T6 |
2 |
|
T7 |
28 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
315339 |
1 |
|
|
T2 |
3 |
|
T6 |
112 |
|
T7 |
708 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
315313 |
1 |
|
|
T2 |
3 |
|
T6 |
112 |
|
T7 |
708 |
auto[1] |
26 |
1 |
|
|
T9 |
4 |
|
T10 |
1 |
|
T71 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2089 |
1 |
|
|
T6 |
1 |
|
T7 |
14 |
|
T8 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6062 |
1 |
|
|
T6 |
2 |
|
T7 |
28 |
|
T8 |
4 |