Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

158095642

1

T1

183

T2

13

T3

3703

full_word

116293266

1

T1

566

T2

135

T3

5599

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	274388648	1			T1	749		T2	148		T3	9302
auto[TlIntgErrCmd]	83	1			T137	3		T138	6		T139	5
auto[TlIntgErrData]	89	1			T137	3		T138	9		T191	2
auto[TlIntgErrBoth]	88	1			T137	4		T138	5		T139	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143174552

1

T1

163

T2

58

T3

6231

auto[1]

131214356

1

T1

586

T2

90

T3

3071

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	97917489	1			T1	147		T2	5		T3	2297
auto[TlIntgErrNone]	partial	auto[1]	60177910	1			T1	36		T2	8		T3	1406
auto[TlIntgErrNone]	full_word	auto[0]	45256941	1			T1	16		T2	53		T3	3934
auto[TlIntgErrNone]	full_word	auto[1]	71036308	1			T1	550		T2	82		T3	1665
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T137	2		T138	2		T139	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T137	1		T138	4		T139	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T192	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T139	1		T193	1		T194	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T137	1		T138	4		T193	4
auto[TlIntgErrData]	partial	auto[1]	36	1			T137	1		T138	5		T191	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T192	1		T194	1		T195	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T137	1		T196	2		T194	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T137	1		T138	3		T139	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T137	3		T138	2		T139	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T197	1		T198	1		-	-