Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1324996335	185042	0	0
RunThenComplete_M	1324996335	2036405	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324996335	185042	0	0
T1	90686	10	0	0
T2	3044	0	0	0
T3	166674	9	0	0
T6	99610	35	0	0
T7	519387	163	0	0
T8	120087	155	0	0
T17	27827	9	0	0
T31	1501	0	0	0
T32	197934	374	0	0
T33	1220	0	0	0
T36	0	5	0	0
T37	0	176	0	0
T48	0	374	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324996335	2036405	0	0
T1	90686	30	0	0
T2	3044	0	0	0
T3	166674	45	0	0
T6	99610	203	0	0
T7	519387	848	0	0
T8	120087	880	0	0
T17	27827	31	0	0
T31	1501	0	0	0
T32	197934	5526	0	0
T33	1220	0	0	0
T36	0	21	0	0
T37	0	434	0	0
T48	0	5526	0	0