Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1326156452	130708	0	0
entropy_period_rd_A	1326156452	1711	0	0
intr_enable_rd_A	1326156452	2269	0	0
prefix_0_rd_A	1326156452	1613	0	0
prefix_10_rd_A	1326156452	1646	0	0
prefix_1_rd_A	1326156452	1623	0	0
prefix_2_rd_A	1326156452	1555	0	0
prefix_3_rd_A	1326156452	1638	0	0
prefix_4_rd_A	1326156452	1639	0	0
prefix_5_rd_A	1326156452	1542	0	0
prefix_6_rd_A	1326156452	1774	0	0
prefix_7_rd_A	1326156452	1723	0	0
prefix_8_rd_A	1326156452	1554	0	0
prefix_9_rd_A	1326156452	1667	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	130708	0	0
T65	787735	109123	0	0
T66	0	18348	0	0
T88	4551	0	0	0
T125	0	117	0	0
T137	0	3	0	0
T138	0	1	0	0
T140	0	189	0	0
T148	0	79	0	0
T150	0	191	0	0
T151	0	5	0	0
T152	0	147	0	0
T153	853493	0	0	0
T154	525798	0	0	0
T155	202020	0	0	0
T156	9515	0	0	0
T157	641656	0	0	0
T158	661324	0	0	0
T159	641578	0	0	0
T160	148060	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1711	0	0
T95	6295	19	0	0
T97	4967	15	0	0
T139	11945	27	0	0
T144	4415	3	0	0
T174	2213	9	0	0
T175	3347	6	0	0
T176	11917	53	0	0
T177	4524	7	0	0
T178	24601	195	0	0
T179	7822	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	2269	0	0
T95	6295	32	0	0
T97	4967	49	0	0
T141	998	8	0	0
T144	4415	9	0	0
T174	2213	19	0	0
T175	3347	9	0	0
T176	11917	92	0	0
T177	4524	14	0	0
T178	24601	184	0	0
T180	916	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1613	0	0
T95	6295	13	0	0
T97	4967	1	0	0
T139	11945	17	0	0
T144	4415	4	0	0
T174	2213	3	0	0
T175	3347	4	0	0
T176	11917	35	0	0
T177	4524	7	0	0
T178	24601	234	0	0
T179	7822	23	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1646	0	0
T97	4967	13	0	0
T139	11945	42	0	0
T174	2213	9	0	0
T175	3347	1	0	0
T176	11917	42	0	0
T177	4524	12	0	0
T178	24601	197	0	0
T179	7822	21	0	0
T181	2800	8	0	0
T182	9307	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1623	0	0
T95	6295	17	0	0
T97	4967	15	0	0
T139	11945	15	0	0
T174	2213	3	0	0
T175	3347	7	0	0
T176	11917	38	0	0
T177	4524	6	0	0
T178	24601	224	0	0
T179	7822	23	0	0
T183	2041	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1555	0	0
T95	6295	29	0	0
T97	4967	10	0	0
T139	11945	35	0	0
T144	4415	9	0	0
T174	2213	3	0	0
T175	3347	6	0	0
T176	11917	54	0	0
T177	4524	5	0	0
T178	24601	209	0	0
T179	7822	20	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1638	0	0
T95	6295	15	0	0
T97	4967	14	0	0
T139	11945	22	0	0
T144	4415	2	0	0
T174	2213	3	0	0
T175	3347	8	0	0
T176	11917	71	0	0
T177	4524	10	0	0
T178	24601	224	0	0
T179	7822	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1639	0	0
T95	6295	11	0	0
T97	4967	8	0	0
T139	11945	19	0	0
T144	4415	4	0	0
T174	2213	5	0	0
T175	3347	11	0	0
T176	11917	68	0	0
T177	4524	7	0	0
T178	24601	228	0	0
T179	7822	20	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1542	0	0
T95	6295	4	0	0
T97	4967	7	0	0
T139	11945	15	0	0
T144	4415	6	0	0
T174	2213	9	0	0
T175	3347	4	0	0
T176	11917	45	0	0
T177	4524	1	0	0
T178	24601	207	0	0
T179	7822	16	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1774	0	0
T95	6295	48	0	0
T97	4967	6	0	0
T139	11945	14	0	0
T174	2213	3	0	0
T175	3347	11	0	0
T176	11917	64	0	0
T177	4524	9	0	0
T178	24601	216	0	0
T179	7822	19	0	0
T181	2800	16	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1723	0	0
T95	6295	36	0	0
T97	4967	16	0	0
T139	11945	16	0	0
T144	4415	7	0	0
T175	3347	12	0	0
T176	11917	58	0	0
T177	4524	13	0	0
T178	24601	237	0	0
T179	7822	8	0	0
T181	2800	15	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1554	0	0
T95	6295	34	0	0
T97	4967	1	0	0
T139	11945	37	0	0
T175	3347	2	0	0
T176	11917	53	0	0
T177	4524	6	0	0
T178	24601	221	0	0
T179	7822	13	0	0
T181	2800	12	0	0
T183	2041	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1326156452	1667	0	0
T95	6295	42	0	0
T97	4967	10	0	0
T139	11945	31	0	0
T144	4415	7	0	0
T174	2213	1	0	0
T175	3347	10	0	0
T176	11917	47	0	0
T177	4524	10	0	0
T178	24601	199	0	0
T179	7822	14	0	0