Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167735795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122283978

1

T1

175736

T2

159

T3

808014

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	151474590	1			T1	227717		T2	74		T3	104327
values[0x0]	66616543	1			T1	106718		T2	51		T3	457300
values[0x1]	71928640	1			T1	115252		T2	47		T3	495481

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130205916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159813857

1

T1

235394

T2

165

T3

107421

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	902539	1			T1	1697		T3	7764		T34	168
valid_sources[0x01]	1697540	1			T1	1735		T3	7599		T34	102
valid_sources[0x02]	868007	1			T1	1790		T3	7640		T34	72
valid_sources[0x03]	1710928	1			T1	1736		T3	7787		T34	103
valid_sources[0x04]	1777964	1			T1	1793		T3	7748		T34	61
valid_sources[0x05]	1195365	1			T1	1780		T3	7812		T34	116
valid_sources[0x06]	901285	1			T1	1645		T3	7668		T34	72
valid_sources[0x07]	888091	1			T1	1681		T3	7801		T34	141
valid_sources[0x08]	864309	1			T1	1720		T3	7781		T34	87
valid_sources[0x09]	916660	1			T1	1718		T3	7913		T34	73
valid_sources[0x0a]	867074	1			T1	1708		T3	7766		T34	110
valid_sources[0x0b]	864586	1			T1	1794		T3	7903		T34	93
valid_sources[0x0c]	1765286	1			T1	1650		T3	7909		T34	94
valid_sources[0x0d]	870210	1			T1	1773		T3	7828		T34	67
valid_sources[0x0e]	869384	1			T1	1769		T3	7806		T34	70
valid_sources[0x0f]	1739218	1			T1	1739		T3	7710		T34	142
valid_sources[0x10]	866935	1			T1	1644		T3	7800		T34	77
valid_sources[0x11]	869808	1			T1	1860		T3	7809		T34	99
valid_sources[0x12]	1033663	1			T1	1826		T3	7783		T34	92
valid_sources[0x13]	867937	1			T1	1826		T3	7882		T34	97
valid_sources[0x14]	903030	1			T1	1782		T3	7791		T34	81
valid_sources[0x15]	1569861	1			T1	1793		T3	7706		T34	89
valid_sources[0x16]	886667	1			T1	1707		T3	7728		T34	134
valid_sources[0x17]	872332	1			T1	1735		T3	7749		T34	116
valid_sources[0x18]	1078357	1			T1	1791		T3	7849		T34	80
valid_sources[0x19]	1852410	1			T1	1840		T3	7830		T34	150
valid_sources[0x1a]	863819	1			T1	1751		T3	7730		T34	122
valid_sources[0x1b]	861414	1			T1	1862		T3	7682		T34	100
valid_sources[0x1c]	981810	1			T1	1667		T3	7725		T34	108
valid_sources[0x1d]	869133	1			T1	1793		T3	7775		T34	126
valid_sources[0x1e]	869567	1			T1	1718		T3	7706		T34	106
valid_sources[0x1f]	863682	1			T1	1789		T3	7834		T34	96
valid_sources[0x20]	861917	1			T1	1727		T3	7869		T34	96
valid_sources[0x21]	1086185	1			T1	1807		T3	7877		T34	127
valid_sources[0x22]	868843	1			T1	1810		T3	7858		T34	67
valid_sources[0x23]	864917	1			T1	1787		T3	7924		T34	105
valid_sources[0x24]	1523585	1			T1	1684		T3	7877		T34	102
valid_sources[0x25]	1512449	1			T1	1719		T3	7802		T34	83
valid_sources[0x26]	874268	1			T1	1743		T3	7829		T34	86
valid_sources[0x27]	885702	1			T1	1829		T3	7725		T34	168
valid_sources[0x28]	864643	1			T1	1777		T3	7828		T34	65
valid_sources[0x29]	865521	1			T1	1612		T3	7760		T34	180
valid_sources[0x2a]	866333	1			T1	1780		T3	7830		T34	70
valid_sources[0x2b]	868105	1			T1	1787		T3	7789		T34	120
valid_sources[0x2c]	2570305	1			T1	1782		T3	7960		T34	105
valid_sources[0x2d]	2143179	1			T1	1718		T3	7788		T34	100
valid_sources[0x2e]	866778	1			T1	1774		T3	7660		T34	129
valid_sources[0x2f]	3326242	1			T1	1748		T3	7859		T34	78
valid_sources[0x30]	868832	1			T1	1809		T3	7677		T34	153
valid_sources[0x31]	871649	1			T1	1719		T3	7856		T34	129
valid_sources[0x32]	868050	1			T1	1731		T3	7844		T34	100
valid_sources[0x33]	883353	1			T1	1707		T3	7886		T34	95
valid_sources[0x34]	868410	1			T1	1762		T3	7646		T34	86
valid_sources[0x35]	865625	1			T1	1694		T3	7824		T34	148
valid_sources[0x36]	867093	1			T1	1781		T3	7688		T34	65
valid_sources[0x37]	868511	1			T1	1674		T3	7835		T34	76
valid_sources[0x38]	1714296	1			T1	1723		T3	7908		T34	109
valid_sources[0x39]	874034	1			T1	1753		T3	7738		T34	112
valid_sources[0x3a]	870165	1			T1	1731		T3	7677		T34	107
valid_sources[0x3b]	1787427	1			T1	1777		T3	7728		T34	111
valid_sources[0x3c]	864457	1			T1	1710		T3	7725		T34	100
valid_sources[0x3d]	1710031	1			T1	1778		T3	7783		T34	109
valid_sources[0x3e]	869405	1			T1	1761		T3	7688		T34	105
valid_sources[0x3f]	865599	1			T1	1781		T3	7882		T34	133
valid_sources[0x40]	875618	1			T1	1705		T3	7763		T34	131
valid_sources[0x41]	1319235	1			T1	1801		T3	7660		T34	95
valid_sources[0x42]	923485	1			T1	1781		T3	7881		T34	102
valid_sources[0x43]	871311	1			T1	1751		T3	7912		T34	111
valid_sources[0x44]	866969	1			T1	1763		T3	7771		T34	92
valid_sources[0x45]	1041656	1			T1	1733		T3	7729		T34	128
valid_sources[0x46]	1923555	1			T1	1738		T3	7741		T34	77
valid_sources[0x47]	1509868	1			T1	1751		T3	7741		T34	82
valid_sources[0x48]	867663	1			T1	1795		T3	7760		T34	140
valid_sources[0x49]	2845899	1			T1	1861		T3	7880		T34	107
valid_sources[0x4a]	1014397	1			T1	1759		T3	7796		T34	90
valid_sources[0x4b]	858858	1			T1	1690		T3	7865		T34	105
valid_sources[0x4c]	863531	1			T1	1692		T3	7864		T34	110
valid_sources[0x4d]	866378	1			T1	1804		T3	7857		T34	119
valid_sources[0x4e]	863781	1			T1	1751		T3	7688		T34	76
valid_sources[0x4f]	975841	1			T1	1867		T3	7809		T34	107
valid_sources[0x50]	1142563	1			T1	1797		T3	7815		T34	86
valid_sources[0x51]	1751190	1			T1	1833		T3	7732		T34	97
valid_sources[0x52]	1542378	1			T1	1687		T3	7917		T34	110
valid_sources[0x53]	865034	1			T1	1676		T3	7787		T34	113
valid_sources[0x54]	863970	1			T1	1795		T3	7674		T34	76
valid_sources[0x55]	865973	1			T1	1771		T3	7736		T34	142
valid_sources[0x56]	870555	1			T1	1773		T3	7689		T34	134
valid_sources[0x57]	873926	1			T1	1707		T3	7822		T34	89
valid_sources[0x58]	863948	1			T1	1721		T3	7790		T34	73
valid_sources[0x59]	926287	1			T1	1735		T3	7752		T34	78
valid_sources[0x5a]	862723	1			T1	1752		T3	7812		T34	131
valid_sources[0x5b]	867043	1			T1	1820		T3	7952		T34	113
valid_sources[0x5c]	2391909	1			T1	1868		T3	7662		T34	98
valid_sources[0x5d]	867547	1			T1	1753		T3	7800		T34	88
valid_sources[0x5e]	863161	1			T1	1708		T3	7788		T34	62
valid_sources[0x5f]	1331611	1			T1	1717		T3	7832		T34	123
valid_sources[0x60]	871776	1			T1	1865		T3	7787		T34	126
valid_sources[0x61]	868982	1			T1	1873		T3	7964		T34	93
valid_sources[0x62]	1246500	1			T1	1797		T3	7782		T34	130
valid_sources[0x63]	2144169	1			T1	1684		T3	7802		T34	75
valid_sources[0x64]	872528	1			T1	1879		T3	7738		T34	126
valid_sources[0x65]	1451276	1			T1	1807		T3	7854		T34	85
valid_sources[0x66]	872819	1			T1	1803		T3	7856		T34	117
valid_sources[0x67]	863836	1			T1	1767		T3	7762		T34	108
valid_sources[0x68]	868716	1			T1	1672		T3	7578		T34	147
valid_sources[0x69]	868315	1			T1	1823		T3	7756		T34	85
valid_sources[0x6a]	870298	1			T1	1807		T3	7923		T34	124
valid_sources[0x6b]	868189	1			T1	1672		T3	7658		T17	1937
valid_sources[0x6c]	864204	1			T1	1745		T3	7677		T34	53
valid_sources[0x6d]	860248	1			T1	1834		T3	7829		T34	63
valid_sources[0x6e]	871357	1			T1	1758		T3	7861		T34	92
valid_sources[0x6f]	868036	1			T1	1885		T3	7801		T34	123
valid_sources[0x70]	875373	1			T1	1765		T3	7770		T34	45
valid_sources[0x71]	1507486	1			T1	1807		T3	7764		T34	96
valid_sources[0x72]	899608	1			T1	1793		T3	7649		T34	105
valid_sources[0x73]	1351238	1			T1	1754		T3	7885		T34	104
valid_sources[0x74]	1163795	1			T1	1831		T3	7746		T34	141
valid_sources[0x75]	870968	1			T1	1752		T3	7943		T34	79
valid_sources[0x76]	881291	1			T1	1834		T3	7703		T34	108
valid_sources[0x77]	913052	1			T1	1776		T3	7798		T34	72
valid_sources[0x78]	905192	1			T1	1788		T3	7815		T34	79
valid_sources[0x79]	862747	1			T1	1751		T3	7811		T34	123
valid_sources[0x7a]	869023	1			T1	1729		T3	7842		T34	56
valid_sources[0x7b]	865066	1			T1	1815		T3	7875		T34	84
valid_sources[0x7c]	863297	1			T1	1749		T3	7634		T34	148
valid_sources[0x7d]	872760	1			T1	1746		T3	7824		T34	80
valid_sources[0x7e]	864582	1			T1	1777		T3	8026		T34	167
valid_sources[0x7f]	862026	1			T1	1693		T3	7874		T34	124
valid_sources[0x80]	863883	1			T1	1763		T3	7890		T34	83

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47594486

1

T1

63219

T2

71

T3

325079

values[0x0]

all_enables

biggest_size

40013248

1

T1

60837

T2

47

T3

261082

values[0x1]

all_enables

biggest_size

34676244

1

T1

51680

T2

41

T3

221853