Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

169507529

1

T1

273951

T2

13

T3

118804

full_word

122394465

1

T1

175736

T2

159

T3

808014

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	291901684	1			T1	449687		T2	172		T3	199606
auto[TlIntgErrCmd]	102	1			T119	4		T120	6		T121	7
auto[TlIntgErrData]	100	1			T119	8		T120	3		T121	6
auto[TlIntgErrBoth]	108	1			T119	8		T120	11		T121	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151891005

1

T1

227717

T2

74

T3

104327

auto[1]

140010989

1

T1

221970

T2

98

T3

952781

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	104264795	1			T1	164498		T2	3		T3	718200
auto[TlIntgErrNone]	partial	auto[1]	65242453	1			T1	109453		T2	10		T3	469846
auto[TlIntgErrNone]	full_word	auto[0]	47626069	1			T1	63219		T2	71		T3	325079
auto[TlIntgErrNone]	full_word	auto[1]	74768367	1			T1	112517		T2	88		T3	482935
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T119	2		T120	1		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T119	2		T120	4		T121	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T120	1		T176	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T121	1		T181	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T121	3		T182	2		T178	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T119	6		T120	3		T121	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T182	1		T183	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	2		T177	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T119	4		T120	7		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T119	4		T120	4		T121	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T175	2		T186	1		T179	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T177	1		T181	1		T179	1