Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1487778680	204670722	0	0
DepthKnown_A	1487778680	1487548293	0	0
RvalidKnown_A	1487778680	1487548293	0	0
WreadyKnown_A	1487778680	1487548293	0	0
gen_passthru_fifo.paramCheckPass	1156	1156	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	204670722	0	0
T1	104373	332385	0	0
T2	3650	85	0	0
T3	525689	144532	0	0
T7	534330	108719	0	0
T13	4502	161	0	0
T17	10335	1465	0	0
T34	143342	13378	0	0
T36	717784	496292	0	0
T37	19109	1279	0	0
T38	34568	3054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1487778680	308631855	0	0
DepthKnown_A	1487778680	1487548293	0	0
RvalidKnown_A	1487778680	1487548293	0	0
WreadyKnown_A	1487778680	1487548293	0	0
gen_passthru_fifo.paramCheckPass	1156	1156	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	308631855	0	0
T1	104373	332385	0	0
T2	3650	85	0	0
T3	525689	144532	0	0
T7	534330	108719	0	0
T13	4502	161	0	0
T17	10335	1465	0	0
T34	143342	13378	0	0
T36	717784	223569	0	0
T37	19109	1279	0	0
T38	34568	3054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1487548293	0	0
T1	104373	104363	0	0
T2	3650	3472	0	0
T3	525689	525681	0	0
T7	534330	534249	0	0
T13	4502	4342	0	0
T17	10335	10237	0	0
T34	143342	143286	0	0
T36	717784	717776	0	0
T37	19109	19022	0	0
T38	34568	34503	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1156	1156	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T34	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0