Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1487778680	311781	0	0
entropy_period_rd_A	1487778680	2049	0	0
intr_enable_rd_A	1487778680	2663	0	0
prefix_0_rd_A	1487778680	1807	0	0
prefix_10_rd_A	1487778680	1982	0	0
prefix_1_rd_A	1487778680	1936	0	0
prefix_2_rd_A	1487778680	1898	0	0
prefix_3_rd_A	1487778680	1878	0	0
prefix_4_rd_A	1487778680	2022	0	0
prefix_5_rd_A	1487778680	1748	0	0
prefix_6_rd_A	1487778680	1833	0	0
prefix_7_rd_A	1487778680	1890	0	0
prefix_8_rd_A	1487778680	1994	0	0
prefix_9_rd_A	1487778680	1939	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	311781	0	0
T24	0	107047	0	0
T48	234008	18297	0	0
T49	0	50387	0	0
T85	0	28875	0	0
T106	131573	0	0	0
T119	0	4	0	0
T120	0	3	0	0
T126	0	104563	0	0
T127	0	124	0	0
T128	0	118	0	0
T129	0	2	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	2049	0	0
T48	234008	53	0	0
T85	0	129	0	0
T93	0	43	0	0
T94	0	67	0	0
T106	131573	0	0	0
T119	0	69	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	38	0	0
T150	0	212	0	0
T151	0	50	0	0
T152	0	33	0	0
T153	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	2663	0	0
T48	234008	53	0	0
T85	0	102	0	0
T93	0	44	0	0
T94	0	85	0	0
T106	131573	0	0	0
T119	0	114	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	8	0	0
T150	0	211	0	0
T151	0	39	0	0
T152	0	16	0	0
T154	0	19	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1807	0	0
T48	234008	67	0	0
T85	0	113	0	0
T93	0	21	0	0
T94	0	64	0	0
T106	131573	0	0	0
T119	0	21	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	28	0	0
T150	0	215	0	0
T151	0	43	0	0
T152	0	19	0	0
T155	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1982	0	0
T48	234008	47	0	0
T85	0	81	0	0
T93	0	19	0	0
T94	0	65	0	0
T106	131573	0	0	0
T119	0	42	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	14	0	0
T150	0	203	0	0
T151	0	42	0	0
T152	0	33	0	0
T155	0	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1936	0	0
T48	234008	60	0	0
T85	0	62	0	0
T93	0	29	0	0
T94	0	67	0	0
T106	131573	0	0	0
T119	0	19	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T150	0	162	0	0
T151	0	21	0	0
T152	0	7	0	0
T153	0	22	0	0
T155	0	3	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1898	0	0
T48	234008	33	0	0
T85	0	72	0	0
T93	0	25	0	0
T94	0	39	0	0
T106	131573	0	0	0
T119	0	44	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	6	0	0
T150	0	205	0	0
T151	0	32	0	0
T155	0	8	0	0
T156	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1878	0	0
T48	234008	59	0	0
T85	0	86	0	0
T93	0	26	0	0
T94	0	38	0	0
T106	131573	0	0	0
T119	0	56	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	36	0	0
T150	0	196	0	0
T151	0	53	0	0
T152	0	3	0	0
T155	0	3	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	2022	0	0
T48	234008	59	0	0
T85	0	114	0	0
T93	0	31	0	0
T94	0	54	0	0
T106	131573	0	0	0
T119	0	51	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	34	0	0
T150	0	207	0	0
T151	0	60	0	0
T152	0	43	0	0
T155	0	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1748	0	0
T48	234008	66	0	0
T85	0	69	0	0
T93	0	20	0	0
T94	0	63	0	0
T106	131573	0	0	0
T119	0	29	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	10	0	0
T150	0	222	0	0
T151	0	36	0	0
T152	0	21	0	0
T153	0	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1833	0	0
T48	234008	55	0	0
T85	0	97	0	0
T93	0	15	0	0
T94	0	62	0	0
T106	131573	0	0	0
T119	0	36	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	45	0	0
T150	0	145	0	0
T151	0	7	0	0
T152	0	29	0	0
T155	0	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1890	0	0
T48	234008	52	0	0
T85	0	116	0	0
T93	0	32	0	0
T94	0	69	0	0
T106	131573	0	0	0
T119	0	37	0	0
T128	0	4	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	29	0	0
T150	0	221	0	0
T151	0	33	0	0
T152	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1994	0	0
T48	234008	59	0	0
T85	0	102	0	0
T93	0	34	0	0
T94	0	50	0	0
T106	131573	0	0	0
T119	0	37	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	3	0	0
T150	0	228	0	0
T151	0	43	0	0
T152	0	33	0	0
T153	0	30	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1487778680	1939	0	0
T48	234008	76	0	0
T85	0	113	0	0
T93	0	31	0	0
T94	0	50	0	0
T106	131573	0	0	0
T119	0	46	0	0
T130	104048	0	0	0
T131	37367	0	0	0
T132	1802	0	0	0
T133	333032	0	0	0
T134	16590	0	0	0
T135	7798	0	0	0
T136	650968	0	0	0
T137	86875	0	0	0
T149	0	5	0	0
T150	0	174	0	0
T151	0	15	0	0
T152	0	19	0	0
T153	0	17	0	0