Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170158554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

125486668

1

T1

175618

T2

342324

T3

70734

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	153220593	1			T1	234359		T2	453749		T3	96733
values[0x0]	68528732	1			T1	109258		T2	216597		T3	19207
values[0x1]	73895897	1			T1	119367		T2	235069		T3	20852

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	132152924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163492298

1

T1

239068

T2

466612

T3

87762

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3226043	1			T1	1768		T2	3648		T3	566
valid_sources[0x01]	934693	1			T1	1757		T2	3448		T3	608
valid_sources[0x02]	963581	1			T1	1818		T2	3573		T3	526
valid_sources[0x03]	916400	1			T1	1846		T2	3631		T3	570
valid_sources[0x04]	918871	1			T1	1821		T2	3699		T3	510
valid_sources[0x05]	917297	1			T1	1759		T2	3554		T3	587
valid_sources[0x06]	924333	1			T1	1809		T2	3490		T3	510
valid_sources[0x07]	921483	1			T1	1818		T2	3530		T3	526
valid_sources[0x08]	918111	1			T1	1825		T2	3528		T3	572
valid_sources[0x09]	1772208	1			T1	1850		T2	3542		T3	483
valid_sources[0x0a]	1193985	1			T1	1798		T2	3604		T3	596
valid_sources[0x0b]	1763740	1			T1	1778		T2	3415		T3	523
valid_sources[0x0c]	1578544	1			T1	1771		T2	3525		T3	526
valid_sources[0x0d]	923850	1			T1	1789		T2	3563		T3	454
valid_sources[0x0e]	919844	1			T1	1908		T2	3500		T3	545
valid_sources[0x0f]	916027	1			T1	1813		T2	3469		T3	486
valid_sources[0x10]	921246	1			T1	1780		T2	3439		T3	672
valid_sources[0x11]	923559	1			T1	1839		T2	3565		T3	534
valid_sources[0x12]	911420	1			T1	1860		T2	3543		T3	600
valid_sources[0x13]	919542	1			T1	1803		T2	3504		T3	500
valid_sources[0x14]	1101252	1			T1	1726		T2	3492		T3	576
valid_sources[0x15]	1573181	1			T1	1811		T2	3594		T3	590
valid_sources[0x16]	920638	1			T1	1841		T2	3445		T3	482
valid_sources[0x17]	918319	1			T1	1795		T2	3531		T3	525
valid_sources[0x18]	1029246	1			T1	1801		T2	3637		T3	541
valid_sources[0x19]	1057899	1			T1	1833		T2	3484		T3	542
valid_sources[0x1a]	919304	1			T1	1797		T2	3415		T3	513
valid_sources[0x1b]	1866985	1			T1	1809		T2	3619		T3	539
valid_sources[0x1c]	1658750	1			T1	1767		T2	3486		T3	497
valid_sources[0x1d]	915547	1			T1	1858		T2	3594		T3	500
valid_sources[0x1e]	919364	1			T1	1808		T2	3458		T3	471
valid_sources[0x1f]	920716	1			T1	1780		T2	3434		T3	473
valid_sources[0x20]	1399899	1			T1	1857		T2	3532		T3	530
valid_sources[0x21]	918079	1			T1	1782		T2	3506		T3	593
valid_sources[0x22]	922367	1			T1	1780		T2	3525		T3	553
valid_sources[0x23]	931042	1			T1	1797		T2	3414		T3	555
valid_sources[0x24]	1369010	1			T1	1778		T2	3665		T3	559
valid_sources[0x25]	1062232	1			T1	1768		T2	3503		T3	577
valid_sources[0x26]	924271	1			T1	1886		T2	3628		T3	535
valid_sources[0x27]	919971	1			T1	1821		T2	3538		T3	547
valid_sources[0x28]	969797	1			T1	1826		T2	3488		T3	586
valid_sources[0x29]	920411	1			T1	1830		T2	3579		T3	497
valid_sources[0x2a]	922854	1			T1	1798		T2	3508		T3	460
valid_sources[0x2b]	925770	1			T1	1824		T2	3463		T3	701
valid_sources[0x2c]	2890958	1			T1	1725		T2	3459		T3	471
valid_sources[0x2d]	1574845	1			T1	1858		T2	3501		T3	530
valid_sources[0x2e]	1588488	1			T1	1753		T2	3562		T3	639
valid_sources[0x2f]	923280	1			T1	1882		T2	3588		T3	545
valid_sources[0x30]	1015168	1			T1	1878		T2	3544		T3	495
valid_sources[0x31]	929986	1			T1	1830		T2	3585		T3	592
valid_sources[0x32]	1569655	1			T1	1883		T2	3565		T3	543
valid_sources[0x33]	921541	1			T1	1837		T2	3554		T3	509
valid_sources[0x34]	918467	1			T1	1793		T2	3555		T3	615
valid_sources[0x35]	921912	1			T1	1865		T2	3558		T3	469
valid_sources[0x36]	914888	1			T1	1815		T2	3449		T3	588
valid_sources[0x37]	963419	1			T1	1815		T2	3549		T3	555
valid_sources[0x38]	2900262	1			T1	1851		T2	3486		T3	594
valid_sources[0x39]	1583029	1			T1	1813		T2	3579		T3	549
valid_sources[0x3a]	1566667	1			T1	1821		T2	3557		T3	561
valid_sources[0x3b]	929986	1			T1	1863		T2	3637		T3	482
valid_sources[0x3c]	921355	1			T1	1904		T2	3498		T3	494
valid_sources[0x3d]	927225	1			T1	1807		T2	3394		T3	457
valid_sources[0x3e]	932187	1			T1	1829		T2	3510		T3	604
valid_sources[0x3f]	927705	1			T1	1861		T2	3520		T3	544
valid_sources[0x40]	922416	1			T1	1831		T2	3630		T3	554
valid_sources[0x41]	936969	1			T1	1805		T2	3607		T3	536
valid_sources[0x42]	915378	1			T1	1808		T2	3539		T3	528
valid_sources[0x43]	1821027	1			T1	1840		T2	3554		T3	580
valid_sources[0x44]	913086	1			T1	1780		T2	3501		T3	488
valid_sources[0x45]	918968	1			T1	1846		T2	3504		T3	584
valid_sources[0x46]	922970	1			T1	1790		T2	3484		T3	575
valid_sources[0x47]	968530	1			T1	1826		T2	3624		T3	561
valid_sources[0x48]	1570200	1			T1	1797		T2	3582		T3	566
valid_sources[0x49]	918946	1			T1	1729		T2	3655		T3	452
valid_sources[0x4a]	929739	1			T1	1778		T2	3480		T3	514
valid_sources[0x4b]	1815464	1			T1	1819		T2	3585		T3	527
valid_sources[0x4c]	916350	1			T1	1841		T2	3489		T3	580
valid_sources[0x4d]	921165	1			T1	1803		T2	3409		T3	629
valid_sources[0x4e]	923556	1			T1	1787		T2	3447		T3	459
valid_sources[0x4f]	922658	1			T1	1859		T2	3549		T3	511
valid_sources[0x50]	924070	1			T1	1809		T2	3488		T3	485
valid_sources[0x51]	911054	1			T1	1772		T2	3606		T3	536
valid_sources[0x52]	926320	1			T1	1807		T2	3442		T3	499
valid_sources[0x53]	1054486	1			T1	1776		T2	3517		T3	474
valid_sources[0x54]	921909	1			T1	1812		T2	3593		T3	456
valid_sources[0x55]	920694	1			T1	1696		T2	3650		T3	541
valid_sources[0x56]	1062607	1			T1	1765		T2	3549		T3	591
valid_sources[0x57]	919114	1			T1	1796		T2	3577		T3	574
valid_sources[0x58]	1088410	1			T1	1756		T2	3597		T3	518
valid_sources[0x59]	918326	1			T1	1755		T2	3442		T3	579
valid_sources[0x5a]	1574823	1			T1	1913		T2	3466		T3	441
valid_sources[0x5b]	921190	1			T1	1766		T2	3534		T3	542
valid_sources[0x5c]	915451	1			T1	1741		T2	3579		T3	469
valid_sources[0x5d]	916876	1			T1	1883		T2	3518		T3	498
valid_sources[0x5e]	2041113	1			T1	1819		T2	3556		T3	601
valid_sources[0x5f]	1080731	1			T1	1820		T2	3513		T3	600
valid_sources[0x60]	1812034	1			T1	1879		T2	3511		T3	532
valid_sources[0x61]	1010360	1			T1	1746		T2	3532		T3	631
valid_sources[0x62]	3329161	1			T1	1722		T2	3458		T3	542
valid_sources[0x63]	1683487	1			T1	1800		T2	3465		T3	643
valid_sources[0x64]	920967	1			T1	1833		T2	3575		T3	546
valid_sources[0x65]	927680	1			T1	1871		T2	3535		T3	521
valid_sources[0x66]	1824109	1			T1	1832		T2	3494		T3	530
valid_sources[0x67]	1820290	1			T1	1844		T2	3532		T3	535
valid_sources[0x68]	1090398	1			T1	1805		T2	3615		T3	612
valid_sources[0x69]	918998	1			T1	1842		T2	3635		T3	433
valid_sources[0x6a]	921941	1			T1	1797		T2	3495		T3	413
valid_sources[0x6b]	936574	1			T1	1830		T2	3533		T3	583
valid_sources[0x6c]	3427167	1			T1	1749		T2	3524		T3	537
valid_sources[0x6d]	919182	1			T1	1862		T2	3528		T3	489
valid_sources[0x6e]	1373663	1			T1	1756		T2	3556		T3	531
valid_sources[0x6f]	995968	1			T1	1873		T2	3482		T3	576
valid_sources[0x70]	925796	1			T1	1910		T2	3511		T3	496
valid_sources[0x71]	918665	1			T1	1832		T2	3556		T3	582
valid_sources[0x72]	1024274	1			T1	1822		T2	3650		T3	558
valid_sources[0x73]	1144264	1			T1	1757		T2	3494		T3	566
valid_sources[0x74]	926266	1			T1	1806		T2	3537		T3	544
valid_sources[0x75]	2676347	1			T1	1830		T2	3509		T3	539
valid_sources[0x76]	915756	1			T1	1785		T2	3468		T3	664
valid_sources[0x77]	2633094	1			T1	1817		T2	3526		T3	533
valid_sources[0x78]	914673	1			T1	1870		T2	3526		T3	498
valid_sources[0x79]	1194788	1			T1	1771		T2	3494		T3	527
valid_sources[0x7a]	1769002	1			T1	1756		T2	3535		T3	514
valid_sources[0x7b]	920461	1			T1	1759		T2	3450		T3	608
valid_sources[0x7c]	920781	1			T1	1850		T2	3537		T3	545
valid_sources[0x7d]	921368	1			T1	1751		T2	3535		T3	581
valid_sources[0x7e]	925428	1			T1	1801		T2	3559		T3	549
valid_sources[0x7f]	922789	1			T1	1829		T2	3506		T3	626
valid_sources[0x80]	918246	1			T1	1831		T2	3546		T3	538

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48373469

1

T1

64719

T2

117717

T3

48562

values[0x0]

all_enables

biggest_size

41292756

1

T1

60382

T2

122070

T3

11798

values[0x1]

all_enables

biggest_size

35820443

1

T1

50517

T2

102537

T3

10374