Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

170537314

1

T1

287366

T2

563091

T3

66058

full_word

125510549

1

T1

175618

T2

342324

T3

70734

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	296047563	1			T1	462984		T2	905415		T3	136792
auto[TlIntgErrCmd]	108	1			T136	6		T138	8		T139	3
auto[TlIntgErrData]	95	1			T136	2		T138	8		T139	4
auto[TlIntgErrBoth]	97	1			T136	2		T138	4		T139	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153307157

1

T1

234359

T2

453749

T3

96733

auto[1]

142740706

1

T1

228625

T2

451666

T3

40059

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	104926867	1			T1	169640		T2	336032		T3	48171
auto[TlIntgErrNone]	partial	auto[1]	65610164	1			T1	117726		T2	227059		T3	17887
auto[TlIntgErrNone]	full_word	auto[0]	48380151	1			T1	64719		T2	117717		T3	48562
auto[TlIntgErrNone]	full_word	auto[1]	77130381	1			T1	110899		T2	224607		T3	22172
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T136	1		T138	4		T139	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T136	5		T138	3		T139	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T138	1		T166	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T165	1		T201	1		T202	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T136	2		T138	5		T139	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T138	3		T139	3		T154	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T203	1		T204	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T136	2		T138	3		T139	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T138	1		T139	1		T154	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T201	1		T205	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T154	1		T206	1		T207	1