Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1436362871	207361	0	0
RunThenComplete_M	1436362871	2176971	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436362871	207361	0	0
T1	506118	246	0	0
T2	210897	390	0	0
T3	356844	123	0	0
T7	893389	155	0	0
T8	840172	81	0	0
T9	0	76	0	0
T13	4893	0	0	0
T33	523150	2265	0	0
T34	11324	9	0	0
T35	2170	0	0	0
T36	106101	246	0	0
T37	0	246	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1436362871	2176971	0	0
T1	506118	5427	0	0
T2	210897	5542	0	0
T3	356844	632	0	0
T7	893389	817	0	0
T8	840172	407	0	0
T9	0	313	0	0
T13	4893	0	0	0
T33	523150	12979	0	0
T34	11324	31	0	0
T35	2170	0	0	0
T36	106101	5427	0	0
T37	0	5427	0	0