Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1437795548	206738746	0	0
DepthKnown_A	1437795548	1437546176	0	0
RvalidKnown_A	1437795548	1437546176	0	0
WreadyKnown_A	1437795548	1437546176	0	0
gen_passthru_fifo.paramCheckPass	1153	1153	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	206738746	0	0
T1	506118	342361	0	0
T2	210897	676591	0	0
T3	356844	80319	0	0
T7	893389	50993	0	0
T8	840172	24359	0	0
T13	4893	126	0	0
T33	523150	142095	0	0
T34	11324	1426	0	0
T35	2170	41	0	0
T36	106101	341173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1437795548	306051272	0	0
DepthKnown_A	1437795548	1437546176	0	0
RvalidKnown_A	1437795548	1437546176	0	0
WreadyKnown_A	1437795548	1437546176	0	0
gen_passthru_fifo.paramCheckPass	1153	1153	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	306051272	0	0
T1	506118	154019	0	0
T2	210897	676591	0	0
T3	356844	80319	0	0
T7	893389	50993	0	0
T8	840172	111667	0	0
T13	4893	583	0	0
T33	523150	142095	0	0
T34	11324	1426	0	0
T35	2170	41	0	0
T36	106101	341173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1437546176	0	0
T1	506118	506112	0	0
T2	210897	210887	0	0
T3	356844	356792	0	0
T7	893389	893300	0	0
T8	840172	840077	0	0
T13	4893	4731	0	0
T33	523150	523140	0	0
T34	11324	11227	0	0
T35	2170	2071	0	0
T36	106101	106093	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0