Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1437795548	67242	0	0
entropy_period_rd_A	1437795548	1883	0	0
intr_enable_rd_A	1437795548	2582	0	0
prefix_0_rd_A	1437795548	1998	0	0
prefix_10_rd_A	1437795548	1953	0	0
prefix_1_rd_A	1437795548	1934	0	0
prefix_2_rd_A	1437795548	1876	0	0
prefix_3_rd_A	1437795548	1950	0	0
prefix_4_rd_A	1437795548	1924	0	0
prefix_5_rd_A	1437795548	1981	0	0
prefix_6_rd_A	1437795548	1988	0	0
prefix_7_rd_A	1437795548	1998	0	0
prefix_8_rd_A	1437795548	2157	0	0
prefix_9_rd_A	1437795548	1885	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	67242	0	0
T25	469637	64520	0	0
T118	0	116	0	0
T119	0	1	0	0
T136	0	2	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	67	0	0
T141	0	141	0	0
T146	0	49	0	0
T155	0	20	0	0
T156	548282	0	0	0
T157	634295	0	0	0
T158	951575	0	0	0
T159	9242	0	0	0
T160	20741	0	0	0
T161	347938	0	0	0
T162	10874	0	0	0
T163	207713	0	0	0
T164	264565	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1883	0	0
T95	12457	99	0	0
T137	12949	73	0	0
T138	26685	111	0	0
T179	5690	17	0	0
T180	3001	13	0	0
T181	5491	18	0	0
T182	3349	8	0	0
T183	2165	5	0	0
T184	2562	16	0	0
T185	7592	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	2582	0	0
T95	12457	121	0	0
T137	12949	128	0	0
T138	26685	197	0	0
T179	5690	7	0	0
T180	3001	6	0	0
T181	5491	35	0	0
T182	3349	18	0	0
T186	960	6	0	0
T187	1222	9	0	0
T188	1040	7	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1998	0	0
T95	12457	48	0	0
T137	12949	51	0	0
T138	26685	58	0	0
T179	5690	11	0	0
T180	3001	3	0	0
T181	5491	10	0	0
T182	3349	11	0	0
T183	2165	3	0	0
T184	2562	7	0	0
T185	7592	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1953	0	0
T95	12457	50	0	0
T137	12949	66	0	0
T138	26685	61	0	0
T179	5690	21	0	0
T180	3001	5	0	0
T181	5491	12	0	0
T182	3349	16	0	0
T183	2165	7	0	0
T184	2562	12	0	0
T185	7592	18	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1934	0	0
T95	12457	43	0	0
T137	12949	78	0	0
T138	26685	78	0	0
T179	5690	6	0	0
T181	5491	17	0	0
T182	3349	1	0	0
T183	2165	8	0	0
T184	2562	17	0	0
T185	7592	6	0	0
T189	8192	16	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1876	0	0
T95	12457	38	0	0
T137	12949	40	0	0
T138	26685	60	0	0
T179	5690	32	0	0
T181	5491	15	0	0
T182	3349	5	0	0
T183	2165	8	0	0
T184	2562	3	0	0
T185	7592	21	0	0
T189	8192	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1950	0	0
T95	12457	48	0	0
T137	12949	64	0	0
T138	26685	69	0	0
T179	5690	7	0	0
T180	3001	4	0	0
T181	5491	24	0	0
T182	3349	5	0	0
T183	2165	8	0	0
T184	2562	5	0	0
T185	7592	12	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1924	0	0
T95	12457	34	0	0
T137	12949	69	0	0
T138	26685	60	0	0
T179	5690	14	0	0
T180	3001	1	0	0
T181	5491	4	0	0
T182	3349	8	0	0
T183	2165	4	0	0
T184	2562	8	0	0
T185	7592	17	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1981	0	0
T95	12457	53	0	0
T137	12949	73	0	0
T138	26685	78	0	0
T179	5690	14	0	0
T180	3001	4	0	0
T181	5491	31	0	0
T182	3349	7	0	0
T183	2165	9	0	0
T184	2562	8	0	0
T185	7592	22	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1988	0	0
T95	12457	74	0	0
T137	12949	73	0	0
T138	26685	92	0	0
T179	5690	5	0	0
T180	3001	10	0	0
T181	5491	11	0	0
T183	2165	1	0	0
T184	2562	3	0	0
T185	7592	7	0	0
T189	8192	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1998	0	0
T95	12457	60	0	0
T137	12949	46	0	0
T138	26685	82	0	0
T179	5690	45	0	0
T180	3001	2	0	0
T181	5491	14	0	0
T182	3349	8	0	0
T184	2562	11	0	0
T185	7592	20	0	0
T189	8192	22	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	2157	0	0
T95	12457	59	0	0
T137	12949	53	0	0
T138	26685	78	0	0
T179	5690	34	0	0
T180	3001	2	0	0
T181	5491	44	0	0
T182	3349	17	0	0
T183	2165	5	0	0
T184	2562	13	0	0
T185	7592	14	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1437795548	1885	0	0
T95	12457	55	0	0
T137	12949	59	0	0
T138	26685	71	0	0
T179	5690	11	0	0
T180	3001	1	0	0
T181	5491	10	0	0
T182	3349	7	0	0
T183	2165	5	0	0
T184	2562	6	0	0
T185	7592	17	0	0