Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186968 |
1 |
|
|
T7 |
2002 |
|
T8 |
420 |
|
T10 |
184 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
105725 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56537 |
1 |
|
|
T7 |
732 |
|
T8 |
413 |
|
T10 |
182 |
seven_bytes |
3536 |
1 |
|
|
T7 |
33 |
|
T71 |
4 |
|
T68 |
59 |
six_bytes |
3491 |
1 |
|
|
T7 |
24 |
|
T71 |
3 |
|
T68 |
61 |
five_bytes |
3481 |
1 |
|
|
T7 |
38 |
|
T71 |
14 |
|
T68 |
61 |
four_bytes |
3495 |
1 |
|
|
T7 |
26 |
|
T71 |
12 |
|
T68 |
53 |
three_bytes |
3552 |
1 |
|
|
T7 |
36 |
|
T71 |
7 |
|
T68 |
61 |
two_bytes |
3563 |
1 |
|
|
T7 |
31 |
|
T71 |
9 |
|
T68 |
54 |
one_byte |
3588 |
1 |
|
|
T7 |
36 |
|
T71 |
3 |
|
T68 |
65 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183600 |
1 |
|
|
T7 |
1964 |
|
T8 |
406 |
|
T10 |
180 |
auto[1] |
3368 |
1 |
|
|
T7 |
38 |
|
T8 |
14 |
|
T10 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186968 |
1 |
|
|
T7 |
2002 |
|
T8 |
420 |
|
T10 |
184 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186958 |
1 |
|
|
T7 |
2002 |
|
T8 |
420 |
|
T10 |
184 |
auto[1] |
10 |
1 |
|
|
T40 |
1 |
|
T60 |
1 |
|
T149 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1070 |
1 |
|
|
T7 |
14 |
|
T8 |
7 |
|
T10 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3368 |
1 |
|
|
T7 |
38 |
|
T8 |
14 |
|
T10 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167166 |
1 |
|
|
T7 |
2390 |
|
T8 |
643 |
|
T38 |
89 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94408 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
50473 |
1 |
|
|
T7 |
527 |
|
T8 |
636 |
|
T38 |
86 |
seven_bytes |
3097 |
1 |
|
|
T7 |
45 |
|
T71 |
16 |
|
T68 |
75 |
six_bytes |
3163 |
1 |
|
|
T7 |
45 |
|
T71 |
25 |
|
T68 |
85 |
five_bytes |
3207 |
1 |
|
|
T7 |
47 |
|
T71 |
23 |
|
T68 |
50 |
four_bytes |
3236 |
1 |
|
|
T7 |
51 |
|
T71 |
26 |
|
T68 |
81 |
three_bytes |
3200 |
1 |
|
|
T7 |
57 |
|
T71 |
27 |
|
T68 |
63 |
two_bytes |
3255 |
1 |
|
|
T7 |
47 |
|
T71 |
32 |
|
T68 |
70 |
one_byte |
3127 |
1 |
|
|
T7 |
60 |
|
T71 |
26 |
|
T68 |
64 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164134 |
1 |
|
|
T7 |
2354 |
|
T8 |
629 |
|
T38 |
83 |
auto[1] |
3032 |
1 |
|
|
T7 |
36 |
|
T8 |
14 |
|
T38 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167166 |
1 |
|
|
T7 |
2390 |
|
T8 |
643 |
|
T38 |
89 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167151 |
1 |
|
|
T7 |
2390 |
|
T8 |
643 |
|
T38 |
89 |
auto[1] |
15 |
1 |
|
|
T40 |
1 |
|
T139 |
1 |
|
T150 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
980 |
1 |
|
|
T7 |
11 |
|
T8 |
7 |
|
T38 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3032 |
1 |
|
|
T7 |
36 |
|
T8 |
14 |
|
T38 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
314622 |
1 |
|
|
T7 |
4099 |
|
T8 |
1371 |
|
T9 |
4 |
auto[1] |
407 |
1 |
|
|
T11 |
30 |
|
T12 |
57 |
|
T13 |
43 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
170536 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
103884 |
1 |
|
|
T7 |
1180 |
|
T8 |
1351 |
|
T9 |
4 |
seven_bytes |
5884 |
1 |
|
|
T7 |
94 |
|
T71 |
32 |
|
T68 |
84 |
six_bytes |
5836 |
1 |
|
|
T7 |
84 |
|
T71 |
36 |
|
T68 |
67 |
five_bytes |
5828 |
1 |
|
|
T7 |
72 |
|
T71 |
34 |
|
T68 |
82 |
four_bytes |
5748 |
1 |
|
|
T7 |
70 |
|
T71 |
24 |
|
T68 |
58 |
three_bytes |
5811 |
1 |
|
|
T7 |
75 |
|
T71 |
33 |
|
T68 |
80 |
two_bytes |
5671 |
1 |
|
|
T7 |
80 |
|
T71 |
31 |
|
T68 |
79 |
one_byte |
5831 |
1 |
|
|
T7 |
75 |
|
T71 |
36 |
|
T68 |
86 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309121 |
1 |
|
|
T7 |
4029 |
|
T8 |
1331 |
|
T9 |
4 |
auto[1] |
5908 |
1 |
|
|
T7 |
70 |
|
T8 |
40 |
|
T10 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
315029 |
1 |
|
|
T7 |
4099 |
|
T8 |
1371 |
|
T9 |
4 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
315012 |
1 |
|
|
T7 |
4099 |
|
T8 |
1371 |
|
T9 |
4 |
auto[1] |
17 |
1 |
|
|
T69 |
1 |
|
T46 |
1 |
|
T151 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2014 |
1 |
|
|
T7 |
23 |
|
T8 |
20 |
|
T10 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
5908 |
1 |
|
|
T7 |
70 |
|
T8 |
40 |
|
T10 |
2 |