Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

175318524

1

T1

7

T2

13661

T3

282307

full_word

128189621

1

T1

6

T2

71878

T3

175570

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	303507855	1			T1	13		T2	85539		T3	457877
auto[TlIntgErrCmd]	84	1			T108	2		T109	5		T110	3
auto[TlIntgErrData]	101	1			T108	12		T109	8		T110	5
auto[TlIntgErrBoth]	105	1			T108	6		T109	7		T110	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157207310

1

T1

1

T2

27792

T3

231811

auto[1]

146300835

1

T1

12

T2

57747

T3

226066

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	107477906	1			T1	1		T2	12776		T3	167721
auto[TlIntgErrNone]	partial	auto[1]	67840357	1			T1	6		T2	885		T3	114586
auto[TlIntgErrNone]	full_word	auto[0]	49729280	1			T2	15016		T3	64090		T18	7598
auto[TlIntgErrNone]	full_word	auto[1]	78460312	1			T1	6		T2	56862		T3	111480
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T108	2		T109	4		T110	3
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T109	1		T138	2		T153	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T156	1		T157	1		T155	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T158	1		T159	1		T154	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T108	6		T109	3		T110	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T108	4		T109	5		T110	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T108	1		T110	1		T158	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T108	1		T153	1		T158	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T108	3		T138	2		T160	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T108	2		T109	6		T110	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T108	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T109	1		T158	2		T159	1