Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1461684414	212749	0	0
RunThenComplete_M	1461684414	2197724	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1461684414	212749	0	0
T2	602750	43	0	0
T3	160922	246	0	0
T4	0	10	0	0
T7	101412	309	0	0
T8	166199	64	0	0
T14	336607	0	0	0
T18	96818	94	0	0
T30	74546	71	0	0
T31	1682	0	0	0
T32	462331	164	0	0
T33	1885	0	0	0
T34	0	130	0	0
T35	0	2337	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1461684414	2197724	0	0
T2	602750	1543	0	0
T3	160922	5427	0	0
T4	0	30	0	0
T7	101412	1458	0	0
T8	166199	357	0	0
T14	336607	0	0	0
T18	96818	226	0	0
T30	74546	177	0	0
T31	1682	0	0	0
T32	462331	432	0	0
T33	1885	0	0	0
T34	0	5001	0	0
T35	0	13147	0	0