Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1463165342	339924	0	0
entropy_period_rd_A	1463165342	2001	0	0
intr_enable_rd_A	1463165342	2764	0	0
prefix_0_rd_A	1463165342	2011	0	0
prefix_10_rd_A	1463165342	2087	0	0
prefix_1_rd_A	1463165342	2020	0	0
prefix_2_rd_A	1463165342	2220	0	0
prefix_3_rd_A	1463165342	1999	0	0
prefix_4_rd_A	1463165342	2124	0	0
prefix_5_rd_A	1463165342	1970	0	0
prefix_6_rd_A	1463165342	2049	0	0
prefix_7_rd_A	1463165342	2098	0	0
prefix_8_rd_A	1463165342	2029	0	0
prefix_9_rd_A	1463165342	2078	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	339924	0	0
T16	171477	17187	0	0
T17	528204	0	0	0
T29	85501	0	0	0
T45	0	85532	0	0
T46	0	56382	0	0
T55	488562	0	0	0
T75	129792	0	0	0
T103	167202	0	0	0
T108	0	3	0	0
T115	0	93640	0	0
T116	0	57904	0	0
T117	0	26277	0	0
T118	0	3	0	0
T119	0	147	0	0
T120	0	272	0	0
T121	203195	0	0	0
T122	12059	0	0	0
T123	91481	0	0	0
T124	334546	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2001	0	0
T92	11793	75	0	0
T108	21575	61	0	0
T109	29061	130	0	0
T118	7937	19	0	0
T132	6023	17	0	0
T133	4997	9	0	0
T134	6871	9	0	0
T135	4405	12	0	0
T136	1519	5	0	0
T137	7630	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2764	0	0
T92	11793	123	0	0
T99	2713	6	0	0
T108	21575	84	0	0
T109	29061	174	0	0
T112	1119	2	0	0
T118	7937	27	0	0
T132	6023	3	0	0
T133	4997	32	0	0
T134	6871	14	0	0
T135	4405	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2011	0	0
T92	11793	44	0	0
T94	2454	9	0	0
T99	2713	5	0	0
T108	21575	50	0	0
T109	29061	76	0	0
T118	7937	19	0	0
T132	6023	18	0	0
T133	4997	13	0	0
T134	6871	28	0	0
T135	4405	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2087	0	0
T92	11793	45	0	0
T94	2454	8	0	0
T99	2713	4	0	0
T108	21575	44	0	0
T109	29061	75	0	0
T118	7937	20	0	0
T132	6023	50	0	0
T133	4997	10	0	0
T134	6871	43	0	0
T135	4405	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2020	0	0
T92	11793	68	0	0
T94	2454	7	0	0
T99	2713	9	0	0
T108	21575	44	0	0
T109	29061	74	0	0
T118	7937	17	0	0
T132	6023	47	0	0
T133	4997	21	0	0
T134	6871	17	0	0
T135	4405	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2220	0	0
T92	11793	43	0	0
T94	2454	2	0	0
T99	2713	8	0	0
T108	21575	49	0	0
T109	29061	90	0	0
T118	7937	20	0	0
T132	6023	32	0	0
T133	4997	13	0	0
T134	6871	39	0	0
T135	4405	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	1999	0	0
T92	11793	64	0	0
T94	2454	12	0	0
T99	2713	8	0	0
T108	21575	43	0	0
T109	29061	69	0	0
T118	7937	17	0	0
T132	6023	20	0	0
T133	4997	14	0	0
T134	6871	25	0	0
T135	4405	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2124	0	0
T92	11793	39	0	0
T94	2454	6	0	0
T99	2713	3	0	0
T108	21575	23	0	0
T109	29061	94	0	0
T118	7937	19	0	0
T132	6023	9	0	0
T133	4997	33	0	0
T134	6871	15	0	0
T135	4405	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	1970	0	0
T92	11793	54	0	0
T94	2454	6	0	0
T99	2713	8	0	0
T108	21575	53	0	0
T109	29061	72	0	0
T118	7937	7	0	0
T132	6023	9	0	0
T133	4997	8	0	0
T134	6871	27	0	0
T135	4405	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2049	0	0
T92	11793	47	0	0
T94	2454	11	0	0
T108	21575	36	0	0
T109	29061	79	0	0
T118	7937	12	0	0
T132	6023	13	0	0
T133	4997	10	0	0
T134	6871	6	0	0
T135	4405	7	0	0
T136	1519	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2098	0	0
T92	11793	82	0	0
T99	2713	4	0	0
T108	21575	56	0	0
T109	29061	73	0	0
T118	7937	15	0	0
T132	6023	31	0	0
T134	6871	23	0	0
T135	4405	9	0	0
T137	7630	2	0	0
T138	10878	28	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2029	0	0
T92	11793	53	0	0
T94	2454	7	0	0
T108	21575	43	0	0
T109	29061	64	0	0
T118	7937	21	0	0
T132	6023	10	0	0
T133	4997	23	0	0
T134	6871	12	0	0
T135	4405	6	0	0
T136	1519	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1463165342	2078	0	0
T92	11793	53	0	0
T94	2454	4	0	0
T108	21575	41	0	0
T109	29061	84	0	0
T118	7937	17	0	0
T132	6023	38	0	0
T133	4997	14	0	0
T134	6871	31	0	0
T135	4405	11	0	0
T136	1519	1	0	0