Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

164317446

1

T1

111499

T2

201

T3

278089

full_word

121241675

1

T1

117077

T2

579

T3

175355

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	285558811	1			T1	228576		T2	780		T3	453444
auto[TlIntgErrCmd]	99	1			T124	7		T125	5		T126	6
auto[TlIntgErrData]	98	1			T124	5		T125	3		T126	7
auto[TlIntgErrBoth]	113	1			T124	8		T125	2		T126	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148026127

1

T1

158458

T2

190

T3

229595

auto[1]

137532994

1

T1

70118

T2

590

T3

223849

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	100648099	1			T1	79787		T2	172		T3	166214
auto[TlIntgErrNone]	partial	auto[1]	63669069	1			T1	31712		T2	29		T3	111875
auto[TlIntgErrNone]	full_word	auto[0]	47377874	1			T1	78671		T2	18		T3	63381
auto[TlIntgErrNone]	full_word	auto[1]	73863769	1			T1	38406		T2	561		T3	111974
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T124	5		T125	3		T126	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T124	1		T125	2		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T124	1		T126	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T178	1		T180	1		T179	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T124	2		T125	1		T126	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T124	3		T125	2		T126	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T126	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T126	1		T174	1		T183	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T124	2		T126	1		T181	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T124	4		T125	2		T126	6
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T124	2		T181	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T175	1		T183	1		T176	1