Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	1417913732	194071	0	0
RunThenComplete_M	1417913732	2091055	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	194071	0	0
T1	573346	192	0	0
T2	74713	10	0	0
T3	335571	246	0	0
T6	503695	148	0	0
T7	37224	11	0	0
T8	122498	15	0	0
T34	528308	2265	0	0
T35	1239	0	0	0
T36	147780	310	0	0
T37	269630	96	0	0
T38	0	77	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1417913732	2091055	0	0
T1	573346	1041	0	0
T2	74713	30	0	0
T3	335571	5427	0	0
T6	503695	661	0	0
T7	37224	50	0	0
T8	122498	78	0	0
T34	528308	12979	0	0
T35	1239	0	0	0
T36	147780	5462	0	0
T37	269630	506	0	0
T38	0	2836	0	0