Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1419225151	258746	0	0
entropy_period_rd_A	1419225151	1578	0	0
intr_enable_rd_A	1419225151	1785	0	0
prefix_0_rd_A	1419225151	1312	0	0
prefix_10_rd_A	1419225151	1354	0	0
prefix_1_rd_A	1419225151	1285	0	0
prefix_2_rd_A	1419225151	1326	0	0
prefix_3_rd_A	1419225151	1307	0	0
prefix_4_rd_A	1419225151	1335	0	0
prefix_5_rd_A	1419225151	1321	0	0
prefix_6_rd_A	1419225151	1258	0	0
prefix_7_rd_A	1419225151	1328	0	0
prefix_8_rd_A	1419225151	1301	0	0
prefix_9_rd_A	1419225151	1345	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	258746	0	0
T29	49457	0	0	0
T49	665003	48333	0	0
T50	0	122293	0	0
T51	0	85081	0	0
T55	1895	0	0	0
T120	202912	0	0	0
T121	20137	0	0	0
T122	1230	0	0	0
T124	0	3	0	0
T125	0	1	0	0
T131	0	2	0	0
T132	0	3	0	0
T133	0	193	0	0
T134	0	74	0	0
T135	0	231	0	0
T137	604402	0	0	0
T138	135505	0	0	0
T139	168997	0	0	0
T140	116339	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1578	0	0
T89	3192	13	0	0
T90	11710	34	0	0
T91	11343	39	0	0
T131	5037	6	0	0
T132	3963	1	0	0
T151	5690	17	0	0
T152	9811	42	0	0
T153	2767	7	0	0
T154	7841	28	0	0
T155	6702	53	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1785	0	0
T89	3192	10	0	0
T90	11710	34	0	0
T91	11343	38	0	0
T131	5037	8	0	0
T132	3963	16	0	0
T136	3899	3	0	0
T151	5690	57	0	0
T152	9811	58	0	0
T153	2767	8	0	0
T154	7841	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1312	0	0
T89	3192	10	0	0
T90	11710	37	0	0
T91	11343	20	0	0
T131	5037	6	0	0
T132	3963	8	0	0
T136	3899	6	0	0
T151	5690	14	0	0
T152	9811	43	0	0
T153	2767	4	0	0
T154	7841	11	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1354	0	0
T89	3192	20	0	0
T90	11710	31	0	0
T91	11343	39	0	0
T131	5037	12	0	0
T132	3963	8	0	0
T136	3899	2	0	0
T151	5690	51	0	0
T152	9811	14	0	0
T153	2767	6	0	0
T154	7841	14	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1285	0	0
T89	3192	9	0	0
T90	11710	33	0	0
T91	11343	36	0	0
T131	5037	10	0	0
T132	3963	8	0	0
T136	3899	3	0	0
T151	5690	20	0	0
T152	9811	9	0	0
T153	2767	7	0	0
T154	7841	16	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1326	0	0
T89	3192	2	0	0
T90	11710	18	0	0
T91	11343	25	0	0
T131	5037	10	0	0
T132	3963	15	0	0
T136	3899	8	0	0
T151	5690	9	0	0
T152	9811	43	0	0
T153	2767	6	0	0
T154	7841	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1307	0	0
T89	3192	13	0	0
T90	11710	49	0	0
T91	11343	12	0	0
T131	5037	8	0	0
T132	3963	5	0	0
T136	3899	14	0	0
T152	9811	18	0	0
T153	2767	12	0	0
T154	7841	19	0	0
T155	6702	21	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1335	0	0
T89	3192	24	0	0
T90	11710	18	0	0
T91	11343	33	0	0
T131	5037	15	0	0
T132	3963	3	0	0
T136	3899	2	0	0
T151	5690	56	0	0
T152	9811	47	0	0
T153	2767	7	0	0
T154	7841	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1321	0	0
T89	3192	17	0	0
T90	11710	21	0	0
T91	11343	29	0	0
T131	5037	8	0	0
T132	3963	15	0	0
T136	3899	3	0	0
T151	5690	33	0	0
T152	9811	7	0	0
T153	2767	7	0	0
T154	7841	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1258	0	0
T89	3192	16	0	0
T90	11710	29	0	0
T91	11343	25	0	0
T131	5037	13	0	0
T132	3963	11	0	0
T136	3899	2	0	0
T151	5690	13	0	0
T152	9811	26	0	0
T153	2767	6	0	0
T154	7841	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1328	0	0
T89	3192	16	0	0
T90	11710	31	0	0
T91	11343	38	0	0
T131	5037	10	0	0
T132	3963	4	0	0
T136	3899	5	0	0
T151	5690	25	0	0
T152	9811	22	0	0
T153	2767	14	0	0
T154	7841	21	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1301	0	0
T89	3192	16	0	0
T90	11710	20	0	0
T91	11343	33	0	0
T131	5037	11	0	0
T132	3963	14	0	0
T136	3899	6	0	0
T151	5690	27	0	0
T152	9811	42	0	0
T153	2767	8	0	0
T154	7841	20	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1419225151	1345	0	0
T89	3192	11	0	0
T90	11710	39	0	0
T91	11343	48	0	0
T131	5037	6	0	0
T132	3963	5	0	0
T136	3899	10	0	0
T151	5690	47	0	0
T152	9811	13	0	0
T153	2767	12	0	0
T154	7841	20	0	0