Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165899 |
1 |
|
|
T1 |
41 |
|
T7 |
36 |
|
T8 |
1089 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86114 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59245 |
1 |
|
|
T1 |
40 |
|
T7 |
35 |
|
T8 |
24 |
seven_bytes |
2854 |
1 |
|
|
T8 |
32 |
|
T20 |
59 |
|
T19 |
59 |
six_bytes |
2915 |
1 |
|
|
T8 |
24 |
|
T20 |
71 |
|
T19 |
49 |
five_bytes |
3007 |
1 |
|
|
T8 |
27 |
|
T20 |
64 |
|
T19 |
53 |
four_bytes |
2939 |
1 |
|
|
T8 |
37 |
|
T20 |
77 |
|
T19 |
40 |
three_bytes |
3002 |
1 |
|
|
T8 |
36 |
|
T20 |
87 |
|
T19 |
50 |
two_bytes |
2886 |
1 |
|
|
T8 |
30 |
|
T20 |
67 |
|
T19 |
38 |
one_byte |
2937 |
1 |
|
|
T8 |
19 |
|
T20 |
70 |
|
T19 |
56 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162741 |
1 |
|
|
T1 |
39 |
|
T7 |
34 |
|
T8 |
1073 |
auto[1] |
3158 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T8 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165899 |
1 |
|
|
T1 |
41 |
|
T7 |
36 |
|
T8 |
1089 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165885 |
1 |
|
|
T1 |
41 |
|
T7 |
36 |
|
T8 |
1089 |
auto[1] |
14 |
1 |
|
|
T173 |
1 |
|
T9 |
1 |
|
T174 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1083 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T8 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3158 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T8 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174040 |
1 |
|
|
T1 |
12 |
|
T7 |
20 |
|
T8 |
1973 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
97065 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
54010 |
1 |
|
|
T1 |
11 |
|
T7 |
19 |
|
T8 |
51 |
seven_bytes |
3294 |
1 |
|
|
T8 |
56 |
|
T20 |
77 |
|
T19 |
38 |
six_bytes |
3329 |
1 |
|
|
T8 |
57 |
|
T20 |
87 |
|
T19 |
49 |
five_bytes |
3290 |
1 |
|
|
T8 |
61 |
|
T20 |
88 |
|
T19 |
45 |
four_bytes |
3288 |
1 |
|
|
T8 |
60 |
|
T20 |
73 |
|
T19 |
58 |
three_bytes |
3347 |
1 |
|
|
T8 |
57 |
|
T20 |
80 |
|
T19 |
49 |
two_bytes |
3248 |
1 |
|
|
T8 |
58 |
|
T20 |
74 |
|
T19 |
54 |
one_byte |
3169 |
1 |
|
|
T8 |
62 |
|
T20 |
80 |
|
T19 |
50 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170849 |
1 |
|
|
T1 |
10 |
|
T7 |
18 |
|
T8 |
1935 |
auto[1] |
3191 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T8 |
38 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174040 |
1 |
|
|
T1 |
12 |
|
T7 |
20 |
|
T8 |
1973 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174033 |
1 |
|
|
T1 |
12 |
|
T7 |
20 |
|
T8 |
1973 |
auto[1] |
7 |
1 |
|
|
T126 |
1 |
|
T175 |
1 |
|
T79 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1028 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T8 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3191 |
1 |
|
|
T1 |
2 |
|
T7 |
2 |
|
T8 |
38 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332504 |
1 |
|
|
T1 |
114 |
|
T7 |
86 |
|
T8 |
4595 |
auto[1] |
465 |
1 |
|
|
T4 |
15 |
|
T9 |
75 |
|
T10 |
86 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
179440 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
110961 |
1 |
|
|
T1 |
113 |
|
T7 |
84 |
|
T8 |
135 |
seven_bytes |
6171 |
1 |
|
|
T8 |
124 |
|
T20 |
127 |
|
T19 |
119 |
six_bytes |
6187 |
1 |
|
|
T8 |
113 |
|
T20 |
154 |
|
T19 |
136 |
five_bytes |
5897 |
1 |
|
|
T8 |
117 |
|
T20 |
149 |
|
T19 |
137 |
four_bytes |
6129 |
1 |
|
|
T8 |
133 |
|
T20 |
154 |
|
T19 |
118 |
three_bytes |
6065 |
1 |
|
|
T8 |
112 |
|
T20 |
136 |
|
T19 |
116 |
two_bytes |
6086 |
1 |
|
|
T8 |
132 |
|
T20 |
139 |
|
T19 |
122 |
one_byte |
6033 |
1 |
|
|
T8 |
128 |
|
T20 |
142 |
|
T19 |
97 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326637 |
1 |
|
|
T1 |
112 |
|
T7 |
82 |
|
T8 |
4533 |
auto[1] |
6332 |
1 |
|
|
T1 |
2 |
|
T7 |
4 |
|
T8 |
62 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332969 |
1 |
|
|
T1 |
114 |
|
T7 |
86 |
|
T8 |
4595 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332937 |
1 |
|
|
T1 |
114 |
|
T7 |
86 |
|
T8 |
4595 |
auto[1] |
32 |
1 |
|
|
T72 |
2 |
|
T103 |
1 |
|
T16 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2119 |
1 |
|
|
T1 |
1 |
|
T7 |
2 |
|
T8 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6332 |
1 |
|
|
T1 |
2 |
|
T7 |
4 |
|
T8 |
62 |