SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[0].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[1].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
push_pull_agent_pkg.uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.cov::m_valid_ready_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 4 | 0 | 4 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_valid_ready | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 53624 | 1 | T1 | 1 | T7 | 2 | T8 | 1325 | ||||
auto[1] | 19341 | 1 | T1 | 1 | T11 | 1 | T7 | 2 | ||||
auto[2] | 301610 | 1 | T1 | 112 | T7 | 82 | T8 | 4519 | ||||
auto[3] | 320085 | 1 | T1 | 113 | T7 | 84 | T8 | 4564 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25527 | 1 | T1 | 1 | T7 | 1 | T8 | 301 | ||||
auto[1] | 9894 | 1 | T1 | 1 | T11 | 1 | T7 | 1 | ||||
auto[2] | 129390 | 1 | T1 | 39 | T7 | 34 | T8 | 1073 | ||||
auto[3] | 138145 | 1 | T1 | 40 | T7 | 35 | T8 | 1081 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 29373 | 1 | T1 | 1 | T7 | 1 | T8 | 19 | ||||
auto[1] | 10180 | 1 | T1 | 1 | T11 | 1 | T7 | 1 | ||||
auto[2] | 135427 | 1 | T1 | 10 | T7 | 18 | T4 | 208 | ||||
auto[3] | 144464 | 1 | T1 | 11 | T7 | 19 | T8 | 552 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |