Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

213474695

1

T1

32016

T2

2445

T3

515836

full_word

153591229

1

T1

47478

T2

11834

T3

345687

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	367065594	1			T1	79494		T2	14279		T3	861523
auto[TlIntgErrCmd]	112	1			T118	5		T134	7		T135	3
auto[TlIntgErrData]	105	1			T118	4		T134	7		T135	2
auto[TlIntgErrBoth]	113	1			T118	11		T134	6		T135	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

191101527

1

T1

51851

T2

8545

T3

430639

auto[1]

175964397

1

T1

27643

T2

5734

T3

430884

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	131068994	1			T1	20251		T2	1394		T3	318817
auto[TlIntgErrNone]	partial	auto[1]	82405397	1			T1	11765		T2	1051		T3	197019
auto[TlIntgErrNone]	full_word	auto[0]	60032384	1			T1	31600		T2	7151		T3	111822
auto[TlIntgErrNone]	full_word	auto[1]	93558819	1			T1	15878		T2	4683		T3	233865
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T118	1		T134	5		T135	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T118	4		T134	2		T135	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T176	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T179	1		T180	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T118	3		T134	5		T176	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T118	1		T134	2		T135	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T182	1		T183	1		T177	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T183	1		T184	2		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T118	4		T134	3		T135	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T118	6		T134	3		T135	3
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T118	1		T135	1		T180	1