Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2109384240	258809073	0	0
DepthKnown_A	2109384240	2109124892	0	0
RvalidKnown_A	2109384240	2109124892	0	0
WreadyKnown_A	2109384240	2109124892	0	0
gen_passthru_fifo.paramCheckPass	1202	1202	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	258809073	0	0
T1	858092	42671	0	0
T2	83090	7211	0	0
T3	946345	644254	0	0
T32	93720	6734	0	0
T33	23864	1328	0	0
T34	202890	680195	0	0
T35	3189	244	0	0
T36	713137	493255	0	0
T37	2138	257	0	0
T38	25514	1385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202	1202	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2109384240	430276526	0	0
DepthKnown_A	2109384240	2109124892	0	0
RvalidKnown_A	2109384240	2109124892	0	0
WreadyKnown_A	2109384240	2109124892	0	0
gen_passthru_fifo.paramCheckPass	1202	1202	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	430276526	0	0
T1	858092	195513	0	0
T2	83090	7211	0	0
T3	946345	290264	0	0
T32	93720	6734	0	0
T33	23864	6080	0	0
T34	202890	680195	0	0
T35	3189	244	0	0
T36	713137	221963	0	0
T37	2138	257	0	0
T38	25514	1385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2109124892	0	0
T1	858092	858030	0	0
T2	83090	83036	0	0
T3	946345	946337	0	0
T32	93720	93640	0	0
T33	23864	23781	0	0
T34	202890	202885	0	0
T35	3189	3137	0	0
T36	713137	713131	0	0
T37	2138	2074	0	0
T38	25514	25451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202	1202	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0