Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2109384240	56369	0	0
entropy_period_rd_A	2109384240	2025	0	0
intr_enable_rd_A	2109384240	2576	0	0
prefix_0_rd_A	2109384240	1427	0	0
prefix_10_rd_A	2109384240	1592	0	0
prefix_1_rd_A	2109384240	1587	0	0
prefix_2_rd_A	2109384240	1616	0	0
prefix_3_rd_A	2109384240	1435	0	0
prefix_4_rd_A	2109384240	1533	0	0
prefix_5_rd_A	2109384240	1449	0	0
prefix_6_rd_A	2109384240	1639	0	0
prefix_7_rd_A	2109384240	1404	0	0
prefix_8_rd_A	2109384240	1611	0	0
prefix_9_rd_A	2109384240	1476	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	56369	0	0
T5	106122	0	0	0
T15	195935	13306	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T23	0	39861	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T118	0	1	0	0
T132	0	178	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	98	0	0
T137	0	253	0	0
T142	0	120	0	0
T143	0	4	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2025	0	0
T5	106122	0	0	0
T15	195935	81	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	6	0	0
T95	0	9	0	0
T97	0	88	0	0
T101	0	20	0	0
T155	0	97	0	0
T156	0	54	0	0
T157	0	3	0	0
T158	0	48	0	0
T159	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	2576	0	0
T5	106122	0	0	0
T15	195935	28	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	1	0	0
T95	0	3	0	0
T101	0	19	0	0
T132	0	3	0	0
T138	0	20	0	0
T155	0	66	0	0
T156	0	2	0	0
T157	0	15	0	0
T160	0	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1427	0	0
T5	106122	0	0	0
T15	195935	71	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	1	0	0
T95	0	1	0	0
T97	0	36	0	0
T101	0	8	0	0
T155	0	28	0	0
T156	0	17	0	0
T158	0	22	0	0
T159	0	2	0	0
T161	0	21	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1592	0	0
T5	106122	0	0	0
T15	195935	31	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	3	0	0
T95	0	11	0	0
T97	0	50	0	0
T101	0	15	0	0
T155	0	49	0	0
T156	0	26	0	0
T158	0	28	0	0
T159	0	7	0	0
T162	0	9	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1587	0	0
T5	106122	0	0	0
T15	195935	57	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	10	0	0
T95	0	16	0	0
T97	0	59	0	0
T101	0	13	0	0
T155	0	62	0	0
T156	0	25	0	0
T158	0	29	0	0
T159	0	8	0	0
T162	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1616	0	0
T5	106122	0	0	0
T15	195935	85	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	1	0	0
T95	0	2	0	0
T97	0	60	0	0
T101	0	22	0	0
T155	0	46	0	0
T156	0	32	0	0
T158	0	11	0	0
T159	0	5	0	0
T162	0	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1435	0	0
T5	106122	0	0	0
T15	195935	63	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	3	0	0
T95	0	6	0	0
T97	0	39	0	0
T101	0	9	0	0
T132	0	3	0	0
T155	0	3	0	0
T156	0	19	0	0
T158	0	24	0	0
T159	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1533	0	0
T5	106122	0	0	0
T15	195935	106	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	7	0	0
T95	0	3	0	0
T97	0	61	0	0
T101	0	23	0	0
T155	0	28	0	0
T156	0	19	0	0
T158	0	21	0	0
T159	0	8	0	0
T162	0	3	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1449	0	0
T5	106122	0	0	0
T15	195935	91	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	2	0	0
T95	0	13	0	0
T97	0	46	0	0
T101	0	10	0	0
T155	0	38	0	0
T156	0	13	0	0
T157	0	7	0	0
T158	0	21	0	0
T159	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1639	0	0
T5	106122	0	0	0
T15	195935	57	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	1	0	0
T95	0	12	0	0
T97	0	50	0	0
T101	0	8	0	0
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T155	0	27	0	0
T156	0	30	0	0
T158	0	30	0	0
T159	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1404	0	0
T5	106122	0	0	0
T15	195935	57	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	6	0	0
T95	0	13	0	0
T97	0	41	0	0
T101	0	9	0	0
T137	0	1	0	0
T155	0	42	0	0
T156	0	8	0	0
T158	0	14	0	0
T159	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1611	0	0
T5	106122	0	0	0
T15	195935	92	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
T61	192849	0	0	0
T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	4	0	0
T95	0	7	0	0
T101	0	6	0	0
T137	0	1	0	0
T155	0	30	0	0
T156	0	55	0	0
T157	0	1	0	0
T158	0	32	0	0
T159	0	4	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2109384240	1476	0	0
T5	106122	0	0	0
T15	195935	57	0	0
T19	722345	0	0	0
T20	161873	0	0	0
T39	104051	0	0	0
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T62	493116	0	0	0
T63	534014	0	0	0
T64	192074	0	0	0
T65	615763	0	0	0
T89	0	7	0	0
T95	0	10	0	0
T97	0	31	0	0
T101	0	12	0	0
T137	0	2	0	0
T155	0	17	0	0
T156	0	9	0	0
T158	0	32	0	0
T159	0	3	0	0