Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165844 |
1 |
|
|
T1 |
440 |
|
T2 |
965 |
|
T7 |
96 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
84067 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61854 |
1 |
|
|
T1 |
436 |
|
T2 |
21 |
|
T7 |
95 |
seven_bytes |
2796 |
1 |
|
|
T2 |
31 |
|
T14 |
36 |
|
T17 |
14 |
six_bytes |
2808 |
1 |
|
|
T2 |
19 |
|
T14 |
38 |
|
T17 |
16 |
five_bytes |
2929 |
1 |
|
|
T2 |
20 |
|
T14 |
44 |
|
T17 |
22 |
four_bytes |
2826 |
1 |
|
|
T2 |
22 |
|
T14 |
37 |
|
T17 |
16 |
three_bytes |
2837 |
1 |
|
|
T2 |
20 |
|
T14 |
37 |
|
T17 |
23 |
two_bytes |
2858 |
1 |
|
|
T2 |
31 |
|
T14 |
56 |
|
T17 |
22 |
one_byte |
2869 |
1 |
|
|
T2 |
29 |
|
T14 |
49 |
|
T17 |
19 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162548 |
1 |
|
|
T1 |
432 |
|
T2 |
955 |
|
T7 |
94 |
auto[1] |
3296 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T7 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165844 |
1 |
|
|
T1 |
440 |
|
T2 |
965 |
|
T7 |
96 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165830 |
1 |
|
|
T1 |
440 |
|
T2 |
965 |
|
T7 |
96 |
auto[1] |
14 |
1 |
|
|
T171 |
1 |
|
T172 |
1 |
|
T173 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1176 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T7 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3296 |
1 |
|
|
T1 |
8 |
|
T2 |
10 |
|
T7 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179703 |
1 |
|
|
T1 |
149 |
|
T2 |
1499 |
|
T14 |
2573 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90912 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67457 |
1 |
|
|
T1 |
146 |
|
T2 |
34 |
|
T14 |
102 |
seven_bytes |
2987 |
1 |
|
|
T2 |
39 |
|
T14 |
61 |
|
T17 |
21 |
six_bytes |
3030 |
1 |
|
|
T2 |
43 |
|
T14 |
50 |
|
T17 |
34 |
five_bytes |
2990 |
1 |
|
|
T2 |
40 |
|
T14 |
57 |
|
T17 |
23 |
four_bytes |
3149 |
1 |
|
|
T2 |
48 |
|
T14 |
71 |
|
T17 |
41 |
three_bytes |
3116 |
1 |
|
|
T2 |
35 |
|
T14 |
75 |
|
T17 |
36 |
two_bytes |
2956 |
1 |
|
|
T2 |
48 |
|
T14 |
63 |
|
T17 |
31 |
one_byte |
3106 |
1 |
|
|
T2 |
32 |
|
T14 |
85 |
|
T17 |
31 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176157 |
1 |
|
|
T1 |
143 |
|
T2 |
1481 |
|
T14 |
2545 |
auto[1] |
3546 |
1 |
|
|
T1 |
6 |
|
T2 |
18 |
|
T14 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179703 |
1 |
|
|
T1 |
149 |
|
T2 |
1499 |
|
T14 |
2573 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179691 |
1 |
|
|
T1 |
149 |
|
T2 |
1499 |
|
T14 |
2573 |
auto[1] |
12 |
1 |
|
|
T174 |
1 |
|
T74 |
1 |
|
T6 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1227 |
1 |
|
|
T1 |
3 |
|
T2 |
2 |
|
T14 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3546 |
1 |
|
|
T1 |
6 |
|
T2 |
18 |
|
T14 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
372111 |
1 |
|
|
T1 |
238 |
|
T2 |
2676 |
|
T14 |
2764 |
auto[1] |
637 |
1 |
|
|
T6 |
79 |
|
T8 |
95 |
|
T9 |
24 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
192189 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
134764 |
1 |
|
|
T1 |
233 |
|
T2 |
69 |
|
T14 |
377 |
seven_bytes |
6710 |
1 |
|
|
T2 |
73 |
|
T14 |
64 |
|
T17 |
42 |
six_bytes |
6638 |
1 |
|
|
T2 |
78 |
|
T14 |
60 |
|
T17 |
52 |
five_bytes |
6619 |
1 |
|
|
T2 |
78 |
|
T14 |
56 |
|
T17 |
47 |
four_bytes |
6503 |
1 |
|
|
T2 |
65 |
|
T14 |
57 |
|
T17 |
47 |
three_bytes |
6464 |
1 |
|
|
T2 |
70 |
|
T14 |
62 |
|
T17 |
40 |
two_bytes |
6443 |
1 |
|
|
T2 |
74 |
|
T14 |
67 |
|
T17 |
44 |
one_byte |
6418 |
1 |
|
|
T2 |
67 |
|
T14 |
69 |
|
T17 |
45 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
365626 |
1 |
|
|
T1 |
228 |
|
T2 |
2644 |
|
T14 |
2726 |
auto[1] |
7122 |
1 |
|
|
T1 |
10 |
|
T2 |
32 |
|
T14 |
38 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
372748 |
1 |
|
|
T1 |
238 |
|
T2 |
2676 |
|
T14 |
2764 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
372728 |
1 |
|
|
T1 |
238 |
|
T2 |
2676 |
|
T14 |
2764 |
auto[1] |
20 |
1 |
|
|
T104 |
1 |
|
T72 |
1 |
|
T74 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2488 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T14 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7122 |
1 |
|
|
T1 |
10 |
|
T2 |
32 |
|
T14 |
38 |