Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

210228151

1

T1

338703

T2

69463

T3

454

full_word

151905311

1

T1

285126

T2

96892

T3

2007

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	362133132	1			T1	623829		T2	166355		T3	2461
auto[TlIntgErrCmd]	128	1			T131	5		T132	5		T133	9
auto[TlIntgErrData]	107	1			T131	4		T132	2		T133	4
auto[TlIntgErrBoth]	95	1			T131	1		T132	3		T133	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187272735

1

T1

375723

T2

110131

T3

1297

auto[1]

174860727

1

T1

248106

T2

56224

T3

1164

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	128104968	1			T1	249399		T2	44503		T3	260
auto[TlIntgErrNone]	partial	auto[1]	82122881	1			T1	89304		T2	24960		T3	194
auto[TlIntgErrNone]	full_word	auto[0]	59167619	1			T1	126324		T2	65628		T3	1037
auto[TlIntgErrNone]	full_word	auto[1]	92737664	1			T1	158802		T2	31264		T3	970
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T131	3		T132	2		T133	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T131	2		T132	3		T133	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T181	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T133	1		T178	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T131	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T131	3		T132	1		T133	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T180	1		T183	1		T184	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T180	1		T185	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T131	1		T133	3		T178	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T132	2		T133	4		T179	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T132	1		T179	1		T185	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T178	1		T177	1		T186	1