Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	277692	0	0
entropy_period_rd_A	2147483647	1789	0	0
intr_enable_rd_A	2147483647	2423	0	0
prefix_0_rd_A	2147483647	1697	0	0
prefix_10_rd_A	2147483647	1847	0	0
prefix_1_rd_A	2147483647	1744	0	0
prefix_2_rd_A	2147483647	1788	0	0
prefix_3_rd_A	2147483647	1741	0	0
prefix_4_rd_A	2147483647	1851	0	0
prefix_5_rd_A	2147483647	1967	0	0
prefix_6_rd_A	2147483647	1756	0	0
prefix_7_rd_A	2147483647	1785	0	0
prefix_8_rd_A	2147483647	1670	0	0
prefix_9_rd_A	2147483647	1875	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	277692	0	0
T16	185934	13196	0	0
T24	0	122821	0	0
T27	334731	0	0	0
T46	0	61274	0	0
T66	3155	0	0	0
T83	0	76909	0	0
T131	0	2	0	0
T132	0	1	0	0
T137	0	358	0	0
T138	0	75	0	0
T139	0	3	0	0
T140	0	76	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T16	185934	48	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	21	0	0
T93	0	9	0	0
T102	0	33	0	0
T132	0	48	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	14	0	0
T160	0	16	0	0
T161	0	11	0	0
T162	0	11	0	0
T163	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T16	185934	39	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	15	0	0
T132	0	78	0	0
T134	0	14	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	19	0	0
T160	0	30	0	0
T161	0	11	0	0
T164	0	26	0	0
T165	0	7	0	0
T166	0	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1697	0	0
T16	185934	58	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	15	0	0
T93	0	5	0	0
T102	0	18	0	0
T132	0	38	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	13	0	0
T160	0	21	0	0
T161	0	4	0	0
T162	0	8	0	0
T163	0	20	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1847	0	0
T16	185934	45	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	28	0	0
T93	0	4	0	0
T102	0	22	0	0
T132	0	36	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	25	0	0
T160	0	6	0	0
T161	0	9	0	0
T162	0	2	0	0
T163	0	19	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1744	0	0
T16	185934	50	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	22	0	0
T93	0	1	0	0
T102	0	25	0	0
T132	0	24	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	1	0	0
T160	0	23	0	0
T161	0	14	0	0
T162	0	1	0	0
T163	0	12	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T16	185934	34	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	23	0	0
T93	0	6	0	0
T102	0	22	0	0
T132	0	42	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	3	0	0
T160	0	18	0	0
T161	0	13	0	0
T162	0	10	0	0
T163	0	24	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1741	0	0
T16	185934	35	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	26	0	0
T93	0	8	0	0
T102	0	20	0	0
T132	0	45	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	47	0	0
T160	0	11	0	0
T161	0	7	0	0
T162	0	7	0	0
T163	0	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1851	0	0
T16	185934	32	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	27	0	0
T93	0	4	0	0
T102	0	22	0	0
T132	0	69	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	25	0	0
T160	0	8	0	0
T161	0	16	0	0
T162	0	15	0	0
T163	0	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T16	185934	72	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	18	0	0
T93	0	9	0	0
T102	0	34	0	0
T132	0	40	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	29	0	0
T160	0	18	0	0
T161	0	9	0	0
T162	0	1	0	0
T163	0	17	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1756	0	0
T16	185934	56	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	19	0	0
T93	0	9	0	0
T102	0	26	0	0
T132	0	40	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	10	0	0
T160	0	15	0	0
T161	0	11	0	0
T162	0	12	0	0
T163	0	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1785	0	0
T16	185934	37	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	19	0	0
T93	0	14	0	0
T102	0	29	0	0
T132	0	47	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T160	0	16	0	0
T161	0	10	0	0
T162	0	16	0	0
T163	0	12	0	0
T167	0	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670	0	0
T16	185934	54	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	25	0	0
T93	0	14	0	0
T102	0	18	0	0
T132	0	36	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	1	0	0
T160	0	21	0	0
T161	0	12	0	0
T162	0	11	0	0
T163	0	16	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T16	185934	38	0	0
T27	334731	0	0	0
T66	3155	0	0	0
T90	0	12	0	0
T93	0	6	0	0
T102	0	27	0	0
T132	0	38	0	0
T141	478239	0	0	0
T142	609352	0	0	0
T143	200257	0	0	0
T144	10565	0	0	0
T145	613220	0	0	0
T146	157942	0	0	0
T147	468598	0	0	0
T159	0	7	0	0
T160	0	22	0	0
T161	0	18	0	0
T162	0	8	0	0
T163	0	17	0	0