Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164997 |
1 |
|
|
T7 |
1636 |
|
T8 |
712 |
|
T5 |
926 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90728 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
52674 |
1 |
|
|
T7 |
51 |
|
T8 |
699 |
|
T5 |
911 |
seven_bytes |
3046 |
1 |
|
|
T7 |
48 |
|
T17 |
66 |
|
T19 |
66 |
six_bytes |
3157 |
1 |
|
|
T7 |
49 |
|
T17 |
58 |
|
T19 |
67 |
five_bytes |
3100 |
1 |
|
|
T7 |
38 |
|
T17 |
57 |
|
T19 |
88 |
four_bytes |
3032 |
1 |
|
|
T7 |
46 |
|
T17 |
45 |
|
T19 |
80 |
three_bytes |
3094 |
1 |
|
|
T7 |
55 |
|
T17 |
48 |
|
T19 |
82 |
two_bytes |
3066 |
1 |
|
|
T7 |
39 |
|
T17 |
61 |
|
T19 |
83 |
one_byte |
3100 |
1 |
|
|
T7 |
42 |
|
T17 |
60 |
|
T19 |
83 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161899 |
1 |
|
|
T7 |
1616 |
|
T8 |
686 |
|
T5 |
896 |
auto[1] |
3098 |
1 |
|
|
T7 |
20 |
|
T8 |
26 |
|
T5 |
30 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164997 |
1 |
|
|
T7 |
1636 |
|
T8 |
712 |
|
T5 |
926 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164989 |
1 |
|
|
T7 |
1636 |
|
T8 |
712 |
|
T5 |
926 |
auto[1] |
8 |
1 |
|
|
T9 |
1 |
|
T185 |
1 |
|
T83 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1024 |
1 |
|
|
T7 |
3 |
|
T8 |
13 |
|
T5 |
15 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3098 |
1 |
|
|
T7 |
20 |
|
T8 |
26 |
|
T5 |
30 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
159936 |
1 |
|
|
T7 |
1478 |
|
T8 |
710 |
|
T5 |
801 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89740 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
48845 |
1 |
|
|
T7 |
48 |
|
T8 |
700 |
|
T5 |
790 |
seven_bytes |
3129 |
1 |
|
|
T7 |
49 |
|
T17 |
60 |
|
T19 |
90 |
six_bytes |
3095 |
1 |
|
|
T7 |
38 |
|
T17 |
57 |
|
T19 |
74 |
five_bytes |
3048 |
1 |
|
|
T7 |
38 |
|
T17 |
44 |
|
T19 |
78 |
four_bytes |
2965 |
1 |
|
|
T7 |
42 |
|
T17 |
51 |
|
T19 |
76 |
three_bytes |
3086 |
1 |
|
|
T7 |
28 |
|
T17 |
59 |
|
T19 |
80 |
two_bytes |
2987 |
1 |
|
|
T7 |
33 |
|
T17 |
31 |
|
T19 |
79 |
one_byte |
3041 |
1 |
|
|
T7 |
37 |
|
T17 |
49 |
|
T19 |
76 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
157014 |
1 |
|
|
T7 |
1460 |
|
T8 |
690 |
|
T5 |
779 |
auto[1] |
2922 |
1 |
|
|
T7 |
18 |
|
T8 |
20 |
|
T5 |
22 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
159936 |
1 |
|
|
T7 |
1478 |
|
T8 |
710 |
|
T5 |
801 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
159928 |
1 |
|
|
T7 |
1478 |
|
T8 |
710 |
|
T5 |
801 |
auto[1] |
8 |
1 |
|
|
T185 |
1 |
|
T186 |
1 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
931 |
1 |
|
|
T7 |
4 |
|
T8 |
10 |
|
T5 |
11 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2922 |
1 |
|
|
T7 |
18 |
|
T8 |
20 |
|
T5 |
22 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333504 |
1 |
|
|
T7 |
2809 |
|
T8 |
1543 |
|
T5 |
1536 |
auto[1] |
344 |
1 |
|
|
T5 |
28 |
|
T9 |
41 |
|
T10 |
27 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
188668 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
100434 |
1 |
|
|
T7 |
80 |
|
T8 |
1516 |
|
T5 |
1536 |
seven_bytes |
6297 |
1 |
|
|
T7 |
71 |
|
T17 |
151 |
|
T19 |
156 |
six_bytes |
6319 |
1 |
|
|
T7 |
70 |
|
T17 |
169 |
|
T19 |
165 |
five_bytes |
6359 |
1 |
|
|
T7 |
65 |
|
T17 |
152 |
|
T19 |
153 |
four_bytes |
6448 |
1 |
|
|
T7 |
78 |
|
T17 |
173 |
|
T19 |
144 |
three_bytes |
6456 |
1 |
|
|
T7 |
84 |
|
T17 |
143 |
|
T19 |
162 |
two_bytes |
6500 |
1 |
|
|
T7 |
70 |
|
T17 |
166 |
|
T19 |
172 |
one_byte |
6367 |
1 |
|
|
T7 |
72 |
|
T17 |
148 |
|
T19 |
145 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327847 |
1 |
|
|
T7 |
2781 |
|
T8 |
1489 |
|
T5 |
1508 |
auto[1] |
6001 |
1 |
|
|
T7 |
28 |
|
T8 |
54 |
|
T5 |
56 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333848 |
1 |
|
|
T7 |
2809 |
|
T8 |
1543 |
|
T5 |
1564 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333830 |
1 |
|
|
T7 |
2809 |
|
T8 |
1543 |
|
T5 |
1564 |
auto[1] |
18 |
1 |
|
|
T18 |
1 |
|
T19 |
1 |
|
T14 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1941 |
1 |
|
|
T7 |
5 |
|
T8 |
27 |
|
T5 |
28 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6001 |
1 |
|
|
T7 |
28 |
|
T8 |
54 |
|
T5 |
56 |