Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

217878091

1

T1

30

T2

30603

T3

551945

full_word

156303134

1

T1

182

T2

41279

T3

342574

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	374180935	1			T1	212		T2	71882		T3	894519
auto[TlIntgErrCmd]	103	1			T101	4		T135	7		T136	7
auto[TlIntgErrData]	101	1			T101	8		T135	6		T136	2
auto[TlIntgErrBoth]	86	1			T101	8		T135	7		T136	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194024983

1

T1

98

T2

47400

T3

448295

auto[1]

180156242

1

T1

114

T2

24482

T3

446224

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	133247182	1			T1	9		T2	19404		T3	331959
auto[TlIntgErrNone]	partial	auto[1]	84630638	1			T1	21		T2	11199		T3	219986
auto[TlIntgErrNone]	full_word	auto[0]	60777663	1			T1	89		T2	27996		T3	116336
auto[TlIntgErrNone]	full_word	auto[1]	95525452	1			T1	93		T2	13283		T3	226238
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T101	3		T135	4		T136	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T101	1		T135	3		T136	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T176	1		T191	1		T190	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T192	1		T145	1		T191	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T101	2		T135	2		T148	7
auto[TlIntgErrData]	partial	auto[1]	44	1			T101	6		T135	3		T139	6
auto[TlIntgErrData]	full_word	auto[0]	2	1			T176	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T135	1		T136	2		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T101	3		T135	4		T148	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T101	4		T135	3		T136	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T189	1		T194	1		T191	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T101	1		T139	1		T195	1