Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2141038495	61113	0	0
entropy_period_rd_A	2141038495	1769	0	0
intr_enable_rd_A	2141038495	2602	0	0
prefix_0_rd_A	2141038495	1741	0	0
prefix_10_rd_A	2141038495	1904	0	0
prefix_1_rd_A	2141038495	1745	0	0
prefix_2_rd_A	2141038495	1789	0	0
prefix_3_rd_A	2141038495	1880	0	0
prefix_4_rd_A	2141038495	1718	0	0
prefix_5_rd_A	2141038495	1847	0	0
prefix_6_rd_A	2141038495	1759	0	0
prefix_7_rd_A	2141038495	1808	0	0
prefix_8_rd_A	2141038495	1677	0	0
prefix_9_rd_A	2141038495	1847	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	61113	0	0
T13	129098	0	0	0
T15	467538	36297	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T68	0	21464	0	0
T80	132201	0	0	0
T101	0	2	0	0
T133	0	2	0	0
T135	0	2	0	0
T136	0	3	0	0
T137	0	40	0	0
T138	0	50	0	0
T146	0	4	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1769	0	0
T13	129098	0	0	0
T15	467538	79	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	32	0	0
T133	0	3	0	0
T148	0	106	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	20	0	0
T166	0	22	0	0
T167	0	2	0	0
T168	0	4	0	0
T169	0	9	0	0
T170	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	2602	0	0
T13	129098	0	0	0
T15	467538	81	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	48	0	0
T133	0	4	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	7	0	0
T166	0	14	0	0
T167	0	1	0	0
T168	0	12	0	0
T171	0	7	0	0
T172	0	32	0	0
T173	0	36	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1741	0	0
T13	129098	0	0	0
T15	467538	114	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	16	0	0
T148	0	71	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	5	0	0
T166	0	8	0	0
T167	0	2	0	0
T168	0	5	0	0
T169	0	2	0	0
T170	0	27	0	0
T174	0	35	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1904	0	0
T13	129098	0	0	0
T15	467538	103	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	13	0	0
T133	0	11	0	0
T148	0	79	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T166	0	39	0	0
T167	0	7	0	0
T168	0	4	0	0
T169	0	8	0	0
T170	0	25	0	0
T174	0	24	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1745	0	0
T13	129098	0	0	0
T15	467538	69	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	28	0	0
T133	0	2	0	0
T148	0	88	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	6	0	0
T166	0	12	0	0
T167	0	2	0	0
T168	0	7	0	0
T169	0	2	0	0
T174	0	12	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1789	0	0
T13	129098	0	0	0
T15	467538	102	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	27	0	0
T133	0	3	0	0
T148	0	80	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	8	0	0
T166	0	19	0	0
T168	0	1	0	0
T169	0	7	0	0
T170	0	26	0	0
T174	0	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1880	0	0
T13	129098	0	0	0
T15	467538	96	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	22	0	0
T148	0	61	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	8	0	0
T166	0	9	0	0
T169	0	1	0	0
T170	0	14	0	0
T174	0	16	0	0
T175	0	7	0	0
T176	0	81	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1718	0	0
T13	129098	0	0	0
T15	467538	95	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	20	0	0
T133	0	3	0	0
T148	0	92	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	2	0	0
T166	0	6	0	0
T167	0	13	0	0
T168	0	3	0	0
T169	0	5	0	0
T174	0	51	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1847	0	0
T13	129098	0	0	0
T15	467538	90	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	23	0	0
T133	0	12	0	0
T148	0	76	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	8	0	0
T166	0	23	0	0
T167	0	3	0	0
T168	0	8	0	0
T170	0	20	0	0
T174	0	38	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1759	0	0
T13	129098	0	0	0
T15	467538	71	0	0
T16	230364	0	0	0
T49	2792	0	0	0
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T102	0	24	0	0
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T150	196813	0	0	0
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T152	10104	0	0	0
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T169	0	1	0	0
T170	0	3	0	0
T174	0	45	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1808	0	0
T13	129098	0	0	0
T15	467538	126	0	0
T16	230364	0	0	0
T49	2792	0	0	0
T80	132201	0	0	0
T102	0	19	0	0
T133	0	9	0	0
T148	0	81	0	0
T149	316334	0	0	0
T150	196813	0	0	0
T151	137323	0	0	0
T152	10104	0	0	0
T153	102895	0	0	0
T154	0	5	0	0
T167	0	6	0	0
T168	0	1	0	0
T169	0	3	0	0
T170	0	8	0	0
T174	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1677	0	0
T13	129098	0	0	0
T15	467538	92	0	0
T16	230364	0	0	0
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T152	10104	0	0	0
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T169	0	8	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141038495	1847	0	0
T13	129098	0	0	0
T15	467538	94	0	0
T16	230364	0	0	0
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