Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

203745886

1

T1

504952

T2

38

T3

36622

full_word

148016906

1

T1

324210

T2

51

T3

53298

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	351762462	1			T1	829162		T2	89		T3	89920
auto[TlIntgErrCmd]	118	1			T130	8		T131	7		T132	7
auto[TlIntgErrData]	99	1			T130	6		T131	6		T132	4
auto[TlIntgErrBoth]	113	1			T130	6		T131	7		T132	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

182546546

1

T1

415957

T2

29

T3

60152

auto[1]

169216246

1

T1

413205

T2

60

T3

29768

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	124682211	1			T1	306900		T2	16		T3	23358
auto[TlIntgErrNone]	partial	auto[1]	79063381	1			T1	198052		T2	22		T3	13264
auto[TlIntgErrNone]	full_word	auto[0]	57864174	1			T1	109057		T2	13		T3	36794
auto[TlIntgErrNone]	full_word	auto[1]	90152696	1			T1	215153		T2	38		T3	16504
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T130	3		T131	4		T132	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T130	5		T131	3		T132	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T164	1		T187	1		T186	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T188	2		T189	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T130	2		T131	2		T132	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T130	3		T131	2		T191	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T130	1		T131	1		T187	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T131	1		T132	1		T192	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T130	2		T131	6		T132	5
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T130	3		T131	1		T132	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T187	1		T186	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T130	1		T132	1		T192	1