Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1913623133	214408	0	0
entropy_period_rd_A	1913623133	1426	0	0
intr_enable_rd_A	1913623133	2058	0	0
prefix_0_rd_A	1913623133	1283	0	0
prefix_10_rd_A	1913623133	1276	0	0
prefix_1_rd_A	1913623133	1265	0	0
prefix_2_rd_A	1913623133	1308	0	0
prefix_3_rd_A	1913623133	1322	0	0
prefix_4_rd_A	1913623133	1327	0	0
prefix_5_rd_A	1913623133	1220	0	0
prefix_6_rd_A	1913623133	1294	0	0
prefix_7_rd_A	1913623133	1254	0	0
prefix_8_rd_A	1913623133	1255	0	0
prefix_9_rd_A	1913623133	1401	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	214408	0	0
T46	699121	94627	0	0
T47	0	15477	0	0
T48	0	17806	0	0
T84	110382	0	0	0
T92	0	83225	0	0
T130	0	5	0	0
T137	0	6	0	0
T138	0	107	0	0
T139	0	9	0	0
T140	0	15	0	0
T141	194437	0	0	0
T142	210615	0	0	0
T143	307816	0	0	0
T144	1284	0	0	0
T145	12926	0	0	0
T146	23043	0	0	0
T147	172594	0	0	0
T148	973449	0	0	0
T149	0	18	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1426	0	0
T48	232968	70	0	0
T92	0	112	0	0
T94	0	23	0	0
T96	0	12	0	0
T97	0	45	0	0
T99	0	73	0	0
T103	0	23	0	0
T131	0	139	0	0
T163	0	9	0	0
T164	0	60	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	2058	0	0
T48	232968	43	0	0
T92	0	95	0	0
T94	0	8	0	0
T96	0	6	0	0
T97	0	42	0	0
T98	0	8	0	0
T131	0	163	0	0
T163	0	2	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0
T174	0	12	0	0
T175	0	20	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1283	0	0
T48	232968	53	0	0
T92	0	71	0	0
T94	0	12	0	0
T96	0	12	0	0
T97	0	27	0	0
T98	0	10	0	0
T99	0	70	0	0
T103	0	3	0	0
T131	0	87	0	0
T164	0	34	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1276	0	0
T48	232968	54	0	0
T92	0	75	0	0
T94	0	13	0	0
T96	0	13	0	0
T97	0	11	0	0
T98	0	15	0	0
T103	0	12	0	0
T131	0	86	0	0
T164	0	55	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0
T176	0	10	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1265	0	0
T48	232968	50	0	0
T92	0	135	0	0
T94	0	26	0	0
T96	0	8	0	0
T97	0	22	0	0
T98	0	10	0	0
T103	0	6	0	0
T131	0	59	0	0
T163	0	5	0	0
T164	0	31	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1308	0	0
T48	232968	48	0	0
T92	0	82	0	0
T94	0	22	0	0
T96	0	15	0	0
T97	0	31	0	0
T98	0	11	0	0
T103	0	10	0	0
T131	0	67	0	0
T163	0	4	0	0
T164	0	53	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1322	0	0
T48	232968	70	0	0
T92	0	76	0	0
T94	0	14	0	0
T96	0	9	0	0
T97	0	10	0	0
T98	0	7	0	0
T103	0	10	0	0
T131	0	98	0	0
T163	0	9	0	0
T164	0	45	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1327	0	0
T48	232968	51	0	0
T92	0	92	0	0
T94	0	4	0	0
T96	0	10	0	0
T97	0	36	0	0
T98	0	5	0	0
T103	0	12	0	0
T131	0	74	0	0
T163	0	16	0	0
T164	0	53	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1220	0	0
T48	232968	66	0	0
T92	0	103	0	0
T94	0	19	0	0
T96	0	7	0	0
T97	0	7	0	0
T98	0	10	0	0
T103	0	5	0	0
T131	0	70	0	0
T163	0	7	0	0
T164	0	38	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1294	0	0
T48	232968	71	0	0
T92	0	124	0	0
T94	0	9	0	0
T96	0	10	0	0
T97	0	39	0	0
T98	0	6	0	0
T99	0	54	0	0
T103	0	16	0	0
T131	0	91	0	0
T164	0	38	0	0
T165	349343	0	0	0
T166	20643	0	0	0
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T168	1059	0	0	0
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T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1254	0	0
T48	232968	37	0	0
T92	0	82	0	0
T94	0	22	0	0
T96	0	11	0	0
T97	0	31	0	0
T98	0	10	0	0
T99	0	66	0	0
T103	0	8	0	0
T131	0	66	0	0
T164	0	39	0	0
T165	349343	0	0	0
T166	20643	0	0	0
T167	2197	0	0	0
T168	1059	0	0	0
T169	84745	0	0	0
T170	443195	0	0	0
T171	4619	0	0	0
T172	329633	0	0	0
T173	611013	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1255	0	0
T48	232968	53	0	0
T92	0	107	0	0
T94	0	11	0	0
T96	0	8	0	0
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T171	4619	0	0	0
T172	329633	0	0	0
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prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1913623133	1401	0	0
T48	232968	62	0	0
T92	0	120	0	0
T94	0	16	0	0
T96	0	12	0	0
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