Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181196 |
1 |
|
|
T2 |
190 |
|
T3 |
21 |
|
T8 |
95 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92305 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67022 |
1 |
|
|
T2 |
186 |
|
T3 |
20 |
|
T8 |
94 |
seven_bytes |
3123 |
1 |
|
|
T13 |
57 |
|
T19 |
49 |
|
T16 |
3 |
six_bytes |
3163 |
1 |
|
|
T13 |
73 |
|
T19 |
41 |
|
T16 |
1 |
five_bytes |
3101 |
1 |
|
|
T13 |
46 |
|
T19 |
39 |
|
T16 |
2 |
four_bytes |
3165 |
1 |
|
|
T13 |
74 |
|
T19 |
40 |
|
T16 |
3 |
three_bytes |
3088 |
1 |
|
|
T13 |
61 |
|
T19 |
54 |
|
T16 |
1 |
two_bytes |
3111 |
1 |
|
|
T13 |
72 |
|
T19 |
43 |
|
T16 |
4 |
one_byte |
3118 |
1 |
|
|
T13 |
61 |
|
T19 |
42 |
|
T16 |
1 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177696 |
1 |
|
|
T2 |
182 |
|
T3 |
19 |
|
T8 |
93 |
auto[1] |
3500 |
1 |
|
|
T2 |
8 |
|
T3 |
2 |
|
T8 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181196 |
1 |
|
|
T2 |
190 |
|
T3 |
21 |
|
T8 |
95 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181181 |
1 |
|
|
T2 |
189 |
|
T3 |
21 |
|
T8 |
95 |
auto[1] |
15 |
1 |
|
|
T2 |
1 |
|
T10 |
1 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1233 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3500 |
1 |
|
|
T2 |
8 |
|
T3 |
2 |
|
T8 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174934 |
1 |
|
|
T2 |
28 |
|
T18 |
122 |
|
T13 |
2060 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86905 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67252 |
1 |
|
|
T2 |
26 |
|
T18 |
121 |
|
T13 |
53 |
seven_bytes |
3048 |
1 |
|
|
T13 |
55 |
|
T19 |
66 |
|
T16 |
8 |
six_bytes |
3014 |
1 |
|
|
T13 |
59 |
|
T19 |
71 |
|
T16 |
4 |
five_bytes |
2944 |
1 |
|
|
T13 |
54 |
|
T19 |
61 |
|
T16 |
9 |
four_bytes |
2985 |
1 |
|
|
T13 |
53 |
|
T19 |
71 |
|
T16 |
9 |
three_bytes |
2941 |
1 |
|
|
T13 |
57 |
|
T19 |
52 |
|
T16 |
9 |
two_bytes |
2922 |
1 |
|
|
T13 |
46 |
|
T19 |
60 |
|
T16 |
8 |
one_byte |
2923 |
1 |
|
|
T13 |
71 |
|
T19 |
66 |
|
T16 |
7 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171501 |
1 |
|
|
T2 |
24 |
|
T18 |
120 |
|
T13 |
2030 |
auto[1] |
3433 |
1 |
|
|
T2 |
4 |
|
T18 |
2 |
|
T13 |
30 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174934 |
1 |
|
|
T2 |
28 |
|
T18 |
122 |
|
T13 |
2060 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174922 |
1 |
|
|
T2 |
27 |
|
T18 |
122 |
|
T13 |
2060 |
auto[1] |
12 |
1 |
|
|
T2 |
1 |
|
T19 |
1 |
|
T9 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1250 |
1 |
|
|
T2 |
2 |
|
T18 |
1 |
|
T13 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3433 |
1 |
|
|
T2 |
4 |
|
T18 |
2 |
|
T13 |
30 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329103 |
1 |
|
|
T2 |
356 |
|
T3 |
30 |
|
T7 |
3 |
auto[1] |
528 |
1 |
|
|
T5 |
4 |
|
T9 |
57 |
|
T10 |
86 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
170665 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
118407 |
1 |
|
|
T2 |
351 |
|
T3 |
29 |
|
T7 |
3 |
seven_bytes |
5873 |
1 |
|
|
T13 |
98 |
|
T19 |
86 |
|
T16 |
53 |
six_bytes |
5645 |
1 |
|
|
T13 |
117 |
|
T19 |
101 |
|
T16 |
45 |
five_bytes |
5866 |
1 |
|
|
T13 |
123 |
|
T19 |
101 |
|
T16 |
42 |
four_bytes |
5822 |
1 |
|
|
T13 |
105 |
|
T19 |
94 |
|
T16 |
53 |
three_bytes |
5757 |
1 |
|
|
T13 |
101 |
|
T19 |
93 |
|
T16 |
55 |
two_bytes |
5854 |
1 |
|
|
T13 |
99 |
|
T19 |
94 |
|
T16 |
47 |
one_byte |
5742 |
1 |
|
|
T13 |
120 |
|
T19 |
79 |
|
T16 |
50 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323232 |
1 |
|
|
T2 |
346 |
|
T3 |
28 |
|
T7 |
3 |
auto[1] |
6399 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T18 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329631 |
1 |
|
|
T2 |
356 |
|
T3 |
30 |
|
T7 |
3 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329618 |
1 |
|
|
T2 |
356 |
|
T3 |
30 |
|
T7 |
3 |
auto[1] |
13 |
1 |
|
|
T103 |
1 |
|
T188 |
1 |
|
T189 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2207 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T18 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6399 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T18 |
2 |