Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48997102

1

T1

24

T2

99466

T3

14364

full_word

47694376

1

T1

199

T2

104435

T3

20750

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	96691178	1			T1	223		T2	203901		T3	35114
auto[TlIntgErrCmd]	91	1			T130	2		T133	4		T134	3
auto[TlIntgErrData]	102	1			T130	7		T133	3		T134	6
auto[TlIntgErrBoth]	107	1			T130	1		T133	3		T134	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53986919

1

T1

86

T2

142094

T3

23012

auto[1]

42704559

1

T1

137

T2

61807

T3

12102

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	33229019	1			T1	12		T2	72599		T3	8918
auto[TlIntgErrNone]	partial	auto[1]	15767803	1			T1	12		T2	26867		T3	5446
auto[TlIntgErrNone]	full_word	auto[0]	20757770	1			T1	74		T2	69495		T3	14094
auto[TlIntgErrNone]	full_word	auto[1]	26936586	1			T1	125		T2	34940		T3	6656
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T130	1		T133	2		T134	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T130	1		T133	2		T134	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T193	1		T194	1		T195	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T134	1		T196	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T130	3		T133	1		T134	2
auto[TlIntgErrData]	partial	auto[1]	50	1			T130	3		T133	1		T134	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T197	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T130	1		T133	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T130	1		T133	1		T134	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T133	1		T134	7		T193	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T178	1		T191	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T133	1		T134	1		T197	1