Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	586855449	56437	0	0
RunThenComplete_M	586855449	736723	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	586855449	56437	0	0
T2	529353	182	0	0
T3	441563	36	0	0
T4	0	6	0	0
T7	3235	0	0	0
T8	384978	34	0	0
T11	2533	0	0	0
T13	0	412	0	0
T18	144414	12	0	0
T32	1645	0	0	0
T33	423611	36	0	0
T34	528397	68	0	0
T35	270631	98	0	0
T37	0	76	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	586855449	736723	0	0
T2	529353	1001	0	0
T3	441563	179	0	0
T4	0	18	0	0
T7	3235	0	0	0
T8	384978	190	0	0
T11	2533	1	0	0
T18	144414	73	0	0
T32	1645	0	0	0
T33	423611	191	0	0
T34	528397	356	0	0
T35	270631	240	0	0
T37	0	2943	0	0