Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588358878	59327304	0	0
DepthKnown_A	588358878	588139463	0	0
RvalidKnown_A	588358878	588139463	0	0
WreadyKnown_A	588358878	588139463	0	0
gen_passthru_fifo.paramCheckPass	868	868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	59327304	0	0
T1	4616	140	0	0
T2	529353	122696	0	0
T3	441563	18721	0	0
T7	3235	84	0	0
T8	384978	19403	0	0
T11	2533	84	0	0
T18	144414	6619	0	0
T32	1645	12	0	0
T33	423611	19847	0	0
T34	528397	37465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	868	868	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	588358878	102795877	0	0
DepthKnown_A	588358878	588139463	0	0
RvalidKnown_A	588358878	588139463	0	0
WreadyKnown_A	588358878	588139463	0	0
gen_passthru_fifo.paramCheckPass	868	868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	102795877	0	0
T1	4616	140	0	0
T2	529353	122696	0	0
T3	441563	85550	0	0
T7	3235	263	0	0
T8	384978	88620	0	0
T11	2533	393	0	0
T18	144414	29859	0	0
T32	1645	53	0	0
T33	423611	89913	0	0
T34	528397	37465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	588139463	0	0
T1	4616	4503	0	0
T2	529353	529298	0	0
T3	441563	441489	0	0
T7	3235	3072	0	0
T8	384978	384891	0	0
T11	2533	2409	0	0
T18	144414	144322	0	0
T32	1645	1576	0	0
T33	423611	423514	0	0
T34	528397	528334	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	868	868	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0