Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588358878	3833	0	0
entropy_period_rd_A	588358878	1431	0	0
intr_enable_rd_A	588358878	2614	0	0
prefix_0_rd_A	588358878	1728	0	0
prefix_10_rd_A	588358878	1673	0	0
prefix_1_rd_A	588358878	1703	0	0
prefix_2_rd_A	588358878	1896	0	0
prefix_3_rd_A	588358878	1808	0	0
prefix_4_rd_A	588358878	1793	0	0
prefix_5_rd_A	588358878	1692	0	0
prefix_6_rd_A	588358878	1754	0	0
prefix_7_rd_A	588358878	1695	0	0
prefix_8_rd_A	588358878	1793	0	0
prefix_9_rd_A	588358878	1709	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	3833	0	0
T29	885433	0	0	0
T47	4053	0	0	0
T54	93919	855	0	0
T85	0	3	0	0
T115	0	2	0	0
T128	0	4	0	0
T129	0	94	0	0
T130	0	1	0	0
T132	0	314	0	0
T141	0	74	0	0
T142	0	83	0	0
T143	0	218	0	0
T151	2873	0	0	0
T152	465881	0	0	0
T153	502569	0	0	0
T154	5148	0	0	0
T155	163920	0	0	0
T156	872761	0	0	0
T157	120140	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1431	0	0
T96	4888	10	0	0
T133	13629	68	0	0
T134	28282	132	0	0
T166	2690	16	0	0
T167	6243	28	0	0
T168	11317	18	0	0
T169	2643	3	0	0
T170	8276	36	0	0
T171	7681	8	0	0
T172	5286	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	2614	0	0
T133	13629	79	0	0
T138	1287	24	0	0
T166	2690	12	0	0
T167	6243	41	0	0
T168	11317	55	0	0
T173	955	14	0	0
T174	1697	6	0	0
T175	1484	2	0	0
T176	1237	7	0	0
T177	1135	25	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1728	0	0
T96	4888	13	0	0
T133	13629	48	0	0
T134	28282	79	0	0
T166	2690	4	0	0
T167	6243	33	0	0
T168	11317	43	0	0
T170	8276	19	0	0
T171	7681	20	0	0
T172	5286	5	0	0
T178	21580	36	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1673	0	0
T96	4888	8	0	0
T133	13629	45	0	0
T134	28282	70	0	0
T166	2690	5	0	0
T167	6243	4	0	0
T168	11317	53	0	0
T170	8276	28	0	0
T171	7681	9	0	0
T172	5286	18	0	0
T178	21580	21	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1703	0	0
T96	4888	8	0	0
T133	13629	38	0	0
T134	28282	80	0	0
T166	2690	5	0	0
T167	6243	22	0	0
T168	11317	30	0	0
T170	8276	16	0	0
T171	7681	21	0	0
T172	5286	19	0	0
T178	21580	37	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1896	0	0
T96	4888	13	0	0
T129	5558	2	0	0
T133	13629	58	0	0
T134	28282	90	0	0
T166	2690	1	0	0
T167	6243	17	0	0
T168	11317	70	0	0
T169	2643	9	0	0
T170	8276	17	0	0
T171	7681	25	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1808	0	0
T96	4888	21	0	0
T133	13629	50	0	0
T134	28282	69	0	0
T166	2690	16	0	0
T167	6243	44	0	0
T168	11317	75	0	0
T169	2643	10	0	0
T170	8276	30	0	0
T171	7681	22	0	0
T172	5286	13	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1793	0	0
T96	4888	1	0	0
T133	13629	46	0	0
T134	28282	85	0	0
T166	2690	10	0	0
T167	6243	2	0	0
T168	11317	63	0	0
T169	2643	15	0	0
T170	8276	23	0	0
T171	7681	19	0	0
T178	21580	65	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1692	0	0
T96	4888	30	0	0
T133	13629	53	0	0
T134	28282	95	0	0
T166	2690	7	0	0
T167	6243	25	0	0
T168	11317	12	0	0
T169	2643	3	0	0
T170	8276	25	0	0
T171	7681	12	0	0
T172	5286	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1754	0	0
T96	4888	6	0	0
T133	13629	35	0	0
T134	28282	92	0	0
T168	11317	48	0	0
T169	2643	5	0	0
T170	8276	16	0	0
T171	7681	16	0	0
T172	5286	17	0	0
T178	21580	38	0	0
T179	7174	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1695	0	0
T96	4888	13	0	0
T133	13629	38	0	0
T134	28282	69	0	0
T167	6243	9	0	0
T168	11317	79	0	0
T170	8276	20	0	0
T171	7681	14	0	0
T172	5286	5	0	0
T178	21580	41	0	0
T179	7174	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1793	0	0
T96	4888	19	0	0
T133	13629	34	0	0
T134	28282	93	0	0
T166	2690	4	0	0
T167	6243	26	0	0
T168	11317	61	0	0
T169	2643	4	0	0
T170	8276	34	0	0
T171	7681	11	0	0
T172	5286	14	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588358878	1709	0	0
T133	13629	45	0	0
T134	28282	69	0	0
T166	2690	7	0	0
T167	6243	7	0	0
T168	11317	41	0	0
T169	2643	1	0	0
T170	8276	22	0	0
T171	7681	20	0	0
T172	5286	7	0	0
T178	21580	32	0	0